ddr2_topecc_auk_ddr_datapath.v

基于SIIGX的PCIe的Kit

      .control_be (be_temp[7 : 6]),
      .control_doing_rd (control_doing_rd),
      .control_doing_wr (control_doing_wr),
      .control_dqs_burst (control_dqs_burst),
      .control_rdata (rdata_temp[63 : 48]),
      .control_wdata (wdata_temp[63 : 48]),
      .control_wdata_valid (control_wdata_valid),
      .ddr_dm (ddr_dm[3]),
      .ddr_dq (ddr_dq[31 : 24]),
      .ddr_dqs (ddr_dqs[3]),
      .dqs_delay_ctrl (dqs_delay_ctrl),
      .dqsupdate (dqsupdate),
      .postamble_clk (postamble_clk_int),
      .reset_n (reset_n),
      .resynch_clk (resynch_clk_int),
      .write_clk (write_clk_int)
    );

  defparam \g_datapath:3:g_ddr_io .gDLL_INPUT_FREQUENCY = "3000ps",
           \g_datapath:3:g_ddr_io .gSTRATIXII_DLL_DELAY_BUFFER_MODE = "high",
           \g_datapath:3:g_ddr_io .gSTRATIXII_DQS_OUT_MODE = "delay_chain3";

  //
  //**********************************
  // DQS group instantiation for dqs[4] 
  assign wdata_temp[79 : 64] = {control_wdata[111 : 104],control_wdata[39 : 32]};
  assign control_rdata[111 : 104] = rdata_temp[79 : 72];
  assign control_rdata[39 : 32] = rdata_temp[71 : 64];
  assign be_temp[9 : 8] = {control_be[13], control_be[4]};
  ddr2_topecc_auk_ddr_dqs_group \g_datapath:4:g_ddr_io 
    (
      .capture_clk (capture_clk_int),
      .clk (clk),
      .control_be (be_temp[9 : 8]),
      .control_doing_rd (control_doing_rd),
      .control_doing_wr (control_doing_wr),
      .control_dqs_burst (control_dqs_burst),
      .control_rdata (rdata_temp[79 : 64]),
      .control_wdata (wdata_temp[79 : 64]),
      .control_wdata_valid (control_wdata_valid),
      .ddr_dm (ddr_dm[4]),
      .ddr_dq (ddr_dq[39 : 32]),
      .ddr_dqs (ddr_dqs[4]),
      .dqs_delay_ctrl (dqs_delay_ctrl),
      .dqsupdate (dqsupdate),
      .postamble_clk (postamble_clk_int),
      .reset_n (reset_n),
      .resynch_clk (resynch_clk_int),
      .write_clk (write_clk_int)
    );

  defparam \g_datapath:4:g_ddr_io .gDLL_INPUT_FREQUENCY = "3000ps",
           \g_datapath:4:g_ddr_io .gSTRATIXII_DLL_DELAY_BUFFER_MODE = "high",
           \g_datapath:4:g_ddr_io .gSTRATIXII_DQS_OUT_MODE = "delay_chain3";

  //
  //**********************************
  // DQS group instantiation for dqs[5] 
  assign wdata_temp[95 : 80] = {control_wdata[119 : 112],control_wdata[47 : 40]};
  assign control_rdata[119 : 112] = rdata_temp[95 : 88];
  assign control_rdata[47 : 40] = rdata_temp[87 : 80];
  assign be_temp[11 : 10] = {control_be[14], control_be[5]};
  ddr2_topecc_auk_ddr_dqs_group \g_datapath:5:g_ddr_io 
    (
      .capture_clk (capture_clk_int),
      .clk (clk),
      .control_be (be_temp[11 : 10]),
      .control_doing_rd (control_doing_rd),
      .control_doing_wr (control_doing_wr),
      .control_dqs_burst (control_dqs_burst),
      .control_rdata (rdata_temp[95 : 80]),
      .control_wdata (wdata_temp[95 : 80]),
      .control_wdata_valid (control_wdata_valid),
      .ddr_dm (ddr_dm[5]),
      .ddr_dq (ddr_dq[47 : 40]),
      .ddr_dqs (ddr_dqs[5]),
      .dqs_delay_ctrl (dqs_delay_ctrl),
      .dqsupdate (dqsupdate),
      .postamble_clk (postamble_clk_int),
      .reset_n (reset_n),
      .resynch_clk (resynch_clk_int),
      .write_clk (write_clk_int)
    );

  defparam \g_datapath:5:g_ddr_io .gDLL_INPUT_FREQUENCY = "3000ps",
           \g_datapath:5:g_ddr_io .gSTRATIXII_DLL_DELAY_BUFFER_MODE = "high",
           \g_datapath:5:g_ddr_io .gSTRATIXII_DQS_OUT_MODE = "delay_chain3";

  //
  //**********************************
  // DQS group instantiation for dqs[6] 
  assign wdata_temp[111 : 96] = {control_wdata[127 : 120],control_wdata[55 : 48]};
  assign control_rdata[127 : 120] = rdata_temp[111 : 104];
  assign control_rdata[55 : 48] = rdata_temp[103 : 96];
  assign be_temp[13 : 12] = {control_be[15], control_be[6]};
  ddr2_topecc_auk_ddr_dqs_group \g_datapath:6:g_ddr_io 
    (
      .capture_clk (capture_clk_int),
      .clk (clk),
      .control_be (be_temp[13 : 12]),
      .control_doing_rd (control_doing_rd),
      .control_doing_wr (control_doing_wr),
      .control_dqs_burst (control_dqs_burst),
      .control_rdata (rdata_temp[111 : 96]),
      .control_wdata (wdata_temp[111 : 96]),
      .control_wdata_valid (control_wdata_valid),
      .ddr_dm (ddr_dm[6]),
      .ddr_dq (ddr_dq[55 : 48]),
      .ddr_dqs (ddr_dqs[6]),
      .dqs_delay_ctrl (dqs_delay_ctrl),
      .dqsupdate (dqsupdate),
      .postamble_clk (postamble_clk_int),
      .reset_n (reset_n),
      .resynch_clk (resynch_clk_int),
      .write_clk (write_clk_int)
    );

  defparam \g_datapath:6:g_ddr_io .gDLL_INPUT_FREQUENCY = "3000ps",
           \g_datapath:6:g_ddr_io .gSTRATIXII_DLL_DELAY_BUFFER_MODE = "high",
           \g_datapath:6:g_ddr_io .gSTRATIXII_DQS_OUT_MODE = "delay_chain3";

  //
  //**********************************
  // DQS group instantiation for dqs[7] 
  assign wdata_temp[127 : 112] = {control_wdata[135 : 128],control_wdata[63 : 56]};
  assign control_rdata[135 : 128] = rdata_temp[127 : 120];
  assign control_rdata[63 : 56] = rdata_temp[119 : 112];
  assign be_temp[15 : 14] = {control_be[16], control_be[7]};
  ddr2_topecc_auk_ddr_dqs_group \g_datapath:7:g_ddr_io 
    (
      .capture_clk (capture_clk_int),
      .clk (clk),
      .control_be (be_temp[15 : 14]),
      .control_doing_rd (control_doing_rd),
      .control_doing_wr (control_doing_wr),
      .control_dqs_burst (control_dqs_burst),
      .control_rdata (rdata_temp[127 : 112]),
      .control_wdata (wdata_temp[127 : 112]),
      .control_wdata_valid (control_wdata_valid),
      .ddr_dm (ddr_dm[7]),
      .ddr_dq (ddr_dq[63 : 56]),
      .ddr_dqs (ddr_dqs[7]),
      .dqs_delay_ctrl (dqs_delay_ctrl),
      .dqsupdate (dqsupdate),
      .postamble_clk (postamble_clk_int),
      .reset_n (reset_n),
      .resynch_clk (resynch_clk_int),
      .write_clk (write_clk_int)
    );

  defparam \g_datapath:7:g_ddr_io .gDLL_INPUT_FREQUENCY = "3000ps",
           \g_datapath:7:g_ddr_io .gSTRATIXII_DLL_DELAY_BUFFER_MODE = "high",
           \g_datapath:7:g_ddr_io .gSTRATIXII_DQS_OUT_MODE = "delay_chain3";

  //
  //**********************************
  // DQS group instantiation for dqs[8] 
  assign wdata_temp[143 : 128] = {control_wdata[143 : 136],control_wdata[71 : 64]};
  assign control_rdata[143 : 136] = rdata_temp[143 : 136];
  assign control_rdata[71 : 64] = rdata_temp[135 : 128];
  assign be_temp[17 : 16] = {control_be[17], control_be[8]};
  ddr2_topecc_auk_ddr_dqs_group \g_datapath:8:g_ddr_io 
    (
      .capture_clk (capture_clk_int),
      .clk (clk),
      .control_be (be_temp[17 : 16]),
      .control_doing_rd (control_doing_rd),
      .control_doing_wr (control_doing_wr),
      .control_dqs_burst (control_dqs_burst),
      .control_rdata (rdata_temp[143 : 128]),
      .control_wdata (wdata_temp[143 : 128]),
      .control_wdata_valid (control_wdata_valid),
      .ddr_dm (ddr_dm[8]),
      .ddr_dq (ddr_dq[71 : 64]),
      .ddr_dqs (ddr_dqs[8]),
      .dqs_delay_ctrl (dqs_delay_ctrl),
      .dqsupdate (dqsupdate),
      .postamble_clk (postamble_clk_int),
      .reset_n (reset_n),
      .resynch_clk (resynch_clk_int),
      .write_clk (write_clk_int)
    );

  defparam \g_datapath:8:g_ddr_io .gDLL_INPUT_FREQUENCY = "3000ps",
           \g_datapath:8:g_ddr_io .gSTRATIXII_DLL_DELAY_BUFFER_MODE = "high",
           \g_datapath:8:g_ddr_io .gSTRATIXII_DQS_OUT_MODE = "delay_chain3";


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  assign #750 write_clk_int = ~clk;
  assign resynch_clk_int = resynch_clk;
  assign #750 postamble_clk_int = ~clk;
  assign capture_clk_int = capture_clk;

//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on
//synthesis read_comments_as_HDL on
//  assign write_clk_int = write_clk;
//  assign resynch_clk_int = resynch_clk;
//  assign postamble_clk_int = postamble_clk;
//  assign capture_clk_int = capture_clk;
//synthesis read_comments_as_HDL off

endmodule