ddr2_topecc_auk_ddr_datapath.v

基于SIIGX的PCIe的Kit

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// synthesis translate_off
`timescale 1ps / 1ps
// synthesis translate_on

// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module ddr2_topecc_auk_ddr_datapath (
                                      // inputs:
                                       capture_clk,
                                       clk,
                                       control_be,
                                       control_doing_rd,
                                       control_doing_wr,
                                       control_dqs_burst,
                                       control_wdata,
                                       control_wdata_valid,
                                       dqs_delay_ctrl,
                                       dqsupdate,
                                       postamble_clk,
                                       reset_n,
                                       resynch_clk,
                                       write_clk,

                                      // outputs:
                                       clk_to_sdram,
                                       clk_to_sdram_n,
                                       control_rdata,
                                       ddr_dm,
                                       ddr_dq,
                                       ddr_dqs
                                    )
;

  parameter gstratixii_dll_delay_buffer_mode = "high";
  parameter gstratixii_dqs_phase = 9000;
  parameter gstratixii_dqs_out_mode = "delay_chain3";


  output  [  2: 0] clk_to_sdram;
  output  [  2: 0] clk_to_sdram_n;
  output  [143: 0] control_rdata;
  output  [  8: 0] ddr_dm;
  inout   [ 71: 0] ddr_dq;
  inout   [  8: 0] ddr_dqs;
  input            capture_clk;
  input            clk;
  input   [ 17: 0] control_be;
  input            control_doing_rd;
  input            control_doing_wr;
  input            control_dqs_burst;
  input   [143: 0] control_wdata;
  input            control_wdata_valid;
  input   [  5: 0] dqs_delay_ctrl;
  input            dqsupdate;
  input            postamble_clk;
  input            reset_n;
  input            resynch_clk;
  input            write_clk;

  wire    [ 17: 0] be_temp;
  wire             capture_clk_int;
  wire    [  2: 0] clk_to_sdram;
  wire    [  2: 0] clk_to_sdram_n;
  wire    [143: 0] control_rdata;
  wire    [  8: 0] ddr_dm;
  wire    [ 71: 0] ddr_dq;
  wire    [  8: 0] ddr_dqs;
  wire             postamble_clk_int;
  wire    [143: 0] rdata_temp;
  wire             resynch_clk_int;
  wire    [143: 0] wdata_temp;
  wire             write_clk_int;
  //
  //************************
  // Clock generator module 
  ddr2_topecc_auk_ddr_clk_gen ddr_clk_gen
    (
      .clk (clk),
      .clk_to_sdram (clk_to_sdram),
      .clk_to_sdram_n (clk_to_sdram_n),
      .reset_n (reset_n)
    );


  //
  //**********************************
  // DQS group instantiation for dqs[0] 
  assign wdata_temp[15 : 0] = {control_wdata[79 : 72],control_wdata[7 : 0]};
  assign control_rdata[79 : 72] = rdata_temp[15 : 8];
  assign control_rdata[7 : 0] = rdata_temp[7 : 0];
  assign be_temp[1 : 0] = {control_be[9], control_be[0]};
  ddr2_topecc_auk_ddr_dqs_group \g_datapath:0:g_ddr_io 
    (
      .capture_clk (capture_clk_int),
      .clk (clk),
      .control_be (be_temp[1 : 0]),
      .control_doing_rd (control_doing_rd),
      .control_doing_wr (control_doing_wr),
      .control_dqs_burst (control_dqs_burst),
      .control_rdata (rdata_temp[15 : 0]),
      .control_wdata (wdata_temp[15 : 0]),
      .control_wdata_valid (control_wdata_valid),
      .ddr_dm (ddr_dm[0]),
      .ddr_dq (ddr_dq[7 : 0]),
      .ddr_dqs (ddr_dqs[0]),
      .dqs_delay_ctrl (dqs_delay_ctrl),
      .dqsupdate (dqsupdate),
      .postamble_clk (postamble_clk_int),
      .reset_n (reset_n),
      .resynch_clk (resynch_clk_int),
      .write_clk (write_clk_int)
    );

  defparam \g_datapath:0:g_ddr_io .gDLL_INPUT_FREQUENCY = "3000ps",
           \g_datapath:0:g_ddr_io .gSTRATIXII_DLL_DELAY_BUFFER_MODE = "high",
           \g_datapath:0:g_ddr_io .gSTRATIXII_DQS_OUT_MODE = "delay_chain3";

  //
  //**********************************
  // DQS group instantiation for dqs[1] 
  assign wdata_temp[31 : 16] = {control_wdata[87 : 80],control_wdata[15 : 8]};
  assign control_rdata[87 : 80] = rdata_temp[31 : 24];
  assign control_rdata[15 : 8] = rdata_temp[23 : 16];
  assign be_temp[3 : 2] = {control_be[10], control_be[1]};
  ddr2_topecc_auk_ddr_dqs_group \g_datapath:1:g_ddr_io 
    (
      .capture_clk (capture_clk_int),
      .clk (clk),
      .control_be (be_temp[3 : 2]),
      .control_doing_rd (control_doing_rd),
      .control_doing_wr (control_doing_wr),
      .control_dqs_burst (control_dqs_burst),
      .control_rdata (rdata_temp[31 : 16]),
      .control_wdata (wdata_temp[31 : 16]),
      .control_wdata_valid (control_wdata_valid),
      .ddr_dm (ddr_dm[1]),
      .ddr_dq (ddr_dq[15 : 8]),
      .ddr_dqs (ddr_dqs[1]),
      .dqs_delay_ctrl (dqs_delay_ctrl),
      .dqsupdate (dqsupdate),
      .postamble_clk (postamble_clk_int),
      .reset_n (reset_n),
      .resynch_clk (resynch_clk_int),
      .write_clk (write_clk_int)
    );

  defparam \g_datapath:1:g_ddr_io .gDLL_INPUT_FREQUENCY = "3000ps",
           \g_datapath:1:g_ddr_io .gSTRATIXII_DLL_DELAY_BUFFER_MODE = "high",
           \g_datapath:1:g_ddr_io .gSTRATIXII_DQS_OUT_MODE = "delay_chain3";

  //
  //**********************************
  // DQS group instantiation for dqs[2] 
  assign wdata_temp[47 : 32] = {control_wdata[95 : 88],control_wdata[23 : 16]};
  assign control_rdata[95 : 88] = rdata_temp[47 : 40];
  assign control_rdata[23 : 16] = rdata_temp[39 : 32];
  assign be_temp[5 : 4] = {control_be[11], control_be[2]};
  ddr2_topecc_auk_ddr_dqs_group \g_datapath:2:g_ddr_io 
    (
      .capture_clk (capture_clk_int),
      .clk (clk),
      .control_be (be_temp[5 : 4]),
      .control_doing_rd (control_doing_rd),
      .control_doing_wr (control_doing_wr),
      .control_dqs_burst (control_dqs_burst),
      .control_rdata (rdata_temp[47 : 32]),
      .control_wdata (wdata_temp[47 : 32]),
      .control_wdata_valid (control_wdata_valid),
      .ddr_dm (ddr_dm[2]),
      .ddr_dq (ddr_dq[23 : 16]),
      .ddr_dqs (ddr_dqs[2]),
      .dqs_delay_ctrl (dqs_delay_ctrl),
      .dqsupdate (dqsupdate),
      .postamble_clk (postamble_clk_int),
      .reset_n (reset_n),
      .resynch_clk (resynch_clk_int),
      .write_clk (write_clk_int)
    );

  defparam \g_datapath:2:g_ddr_io .gDLL_INPUT_FREQUENCY = "3000ps",
           \g_datapath:2:g_ddr_io .gSTRATIXII_DLL_DELAY_BUFFER_MODE = "high",
           \g_datapath:2:g_ddr_io .gSTRATIXII_DQS_OUT_MODE = "delay_chain3";

  //
  //**********************************
  // DQS group instantiation for dqs[3] 
  assign wdata_temp[63 : 48] = {control_wdata[103 : 96],control_wdata[31 : 24]};
  assign control_rdata[103 : 96] = rdata_temp[63 : 56];
  assign control_rdata[31 : 24] = rdata_temp[55 : 48];
  assign be_temp[7 : 6] = {control_be[12], control_be[3]};
  ddr2_topecc_auk_ddr_dqs_group \g_datapath:3:g_ddr_io 
    (
      .capture_clk (capture_clk_int),
      .clk (clk),