ddr2_topecc_ddr_settings.txt

基于SIIGX的PCIe的Kit

mem_type=ddr2_sdram
tcl_pin_file=
megawizard_version=3.4.0
clock_generation=ddio
memory_device=Custom
override_resync_phase= 272
override_capture_phase= -1
override_postamble_phase= 90
manual_hierarchy_control=false
parse_example_design=true
pf_pin_load_on_dq=4
pf_pin_load_on_cmd=2
pf_pin_load_on_clk=2
clockfeedback_in_pin_name=fedback_clk_in
fedback_clock_mode=false
tpd_clockfeedback_trace_nom=2000
family=stratixiigx
local_data_bits=144
mem_dq_per_dqs=8
mem_chip_bits=0
enable_capture_clk=false
enable_resynch_clk=true
chosen_resynch_clk=dedicated
chosen_resynch_edge=rising
chosen_resynch_cycle=4
inter_resynch=true
chosen_capture_clk=dedicated
chosen_capture_edge=rising
chosen_postamble_clk=write_clk
chosen_postamble_edge=falling
chosen_postamble_cycle=4
inter_postamble=false
pipeline_readdata=true
postamble_regs=1
stratix_undelayeddqsout_insert_buffers=0
clock_period_in_ps=3000
dqs_phase=72
local_avalon_if=false
mem_chipsels=1
mem_bank_bits=2
mem_row_bits=13
mem_col_bits=10
mem_pch_bit=10
local_burst_len=2
local_burst_len_bits=2
user_refresh=false
num_output_clocks=3
toplevel_name=ddr2_v340_ecc
wrapper_name=ddr2_topecc
ddr_pin_prefix=ddr2_
//From old ddr_settings file
current_script_working_dir=c:/altera/megacore/ddr_ddr2_sdram-v3.4.0/system_timing
current_quartus_project_dir=C:/cvs_sandbox/boards/stratix2_gx/stratix2_gx_pciex/pld/ddr2/ddr2_v340_ecc/
enable_postamble=true
quartus_project_name=ddr2_v340_ecc
quartus_version=6.0
device=EP2SGX90F
speed_grade=C3
mig_device=NONE
mig_package=NONE
mig_speed_grade=NONE
mig_family=NONE
clock_freq_in_mhz=333.333
cas_latency=5.0
ddr_mode=normal
use_dedicated_pll_output_as_clock=0
dll_ref_clock__switched_off_during_reads=false
tPD_clock_trace_NOM=752
tPD_dqs_trace_total_NOM=306
pcb_delay_var_percent=2
board_tSKEW_data_group=17
tPD_fedback_clock_NOM=2000
memory_tDQSQ=240
memory_tQHS=340
memory_tDQSCK=400
memory_tAC=450
memory_fmax_at_cl5=0.0
memory_fmax_at_cl4=0.0
memory_fmax_at_cl3=200.0
memory_fmax_at_cl25=167.0
memory_fmax_at_cl2=134.0
memory_tCK_MAX=8000
memory_tDS=100
memory_tDH=175
memory_percent_tDQSS=75
override_resynch_was_used=false
override_capture_was_used=false
override_postamble_was_used=false
dqs_delay_cyclone=
project_path=C:/cvs_sandbox/boards/stratix2_gx/stratix2_gx_pciex/pld/ddr2/ddr2_v340_ecc/
wrapper_path=C:/cvs_sandbox/boards/stratix2_gx/stratix2_gx_pciex/pld/ddr2/ddr2_v340_ecc
mw_path=c:/altera/megacore/ddr_ddr2_sdram-v3.4.0/system_timing
//From user_assignments.txt
memory_type=ddr2_sdram
memory_width=72
package=F1508
instance_name_1=ddr2_topecc
v=0
byte_groups = 0B 2B 4B 6B 8B 10B 12B 14B 16B
buffer_DLL_delay_output=false
use_dqs_for_read=true
language=verilog
tinit_clocks=65534
rtl_roundtrip_clocks=1.5055555555555555
variation_path=Automatically extracted by Quartus synthesis|
clock_pos_pin_name=clk_to_sdram_p[0]
clock_neg_pin_name=clk_to_sdram_n[0]
stratixii_dqs_phase=9000
stratixii_dll_delay_buffer_mode=high
stratixii_dqs_out_mode=delay_chain3
stratixii_dll_delay_chain_length=12
reg_dimm=false
negedge_addrcmd =true
extra_pl_reg=true
migratable_bytegroups=true
include_x4_dm_pins=true
mem_odt_ranks=1
chosen_resynch_cycle=4
chosen_postamble_phase=90
dqs_cram_cyclone=
chosen_resynch_phase=272
family_is_stratix=false
chosen_postamble_cycle=4
family_is_stratix2=true
family_is_cyclone2=false
best_dqs_shift_setting=0