ddr2_topecc_estimated_data.dat

基于SIIGX的PCIe的Kit

# Estimated data for Pre-Compile
set min_paths_for_each_half_dq_0(reg_2_post) 706
set min_paths_for_each_half_dq_0(post_2_dqsclk) 112
set min_paths_for_each_half_dq_0(dqsclk_2_post) 413
set min_paths_for_each_half_dq_0(dq_2_ddio) 1143
set min_paths_for_each_half_dq_0(ddio_2_core) 0
set min_paths_for_each_half_dq_0(clk_2_pin) 852
set min_paths_for_each_half_dq_0(dqsclk_2_ddio_resync) 413
# set min_paths_for_each_half_dq_0(dqspin_2_dqsclk) 1452
set min_paths_for_each_half_dq_0(core_2_reg) 97

set max_paths_for_each_half_dq_0(reg_2_post) 1444
set max_paths_for_each_half_dq_0(post_2_dqsclk) 164
set max_paths_for_each_half_dq_0(dqsclk_2_post) 649
set max_paths_for_each_half_dq_0(dq_2_ddio) 1738
set max_paths_for_each_half_dq_0(ddio_2_core) 1263
set max_paths_for_each_half_dq_0(clk_2_pin) 1423
set max_paths_for_each_half_dq_0(dqsclk_2_ddio_resync) 649
# set max_paths_for_each_half_dq_0(dqspin_2_dqsclk) 1798
set max_paths_for_each_half_dq_0(core_2_reg) 1293