hello_gx.map.rpt

基于SIIGX的PCIe的Kit

; Allow Any ROM Size For Recognition                         ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition              ; Off                ; Off                ;
; Maximum Number of M512 Memory Blocks                       ; Unlimited          ; Unlimited          ;
; Maximum Number of M4K Memory Blocks                        ; Unlimited          ; Unlimited          ;
; Maximum Number of M-RAM Memory Blocks                      ; Unlimited          ; Unlimited          ;
; Ignore translate_off and translate_on Synthesis Directives ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report         ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                         ; Off                ; Off                ;
; Retiming Meta-Stability Register Sequence Length           ; 2                  ; 2                  ;
; PowerPlay Power Optimization                               ; Normal compilation ; Normal compilation ;
; HDL message level                                          ; Level2             ; Level2             ;
+------------------------------------------------------------+--------------------+--------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                                      ;
+----------------------------------+-----------------+------------------------+-----------------------------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path                                                                  ;
+----------------------------------+-----------------+------------------------+-----------------------------------------------------------------------------------------------+
; hello_gx.v                       ; yes             ; User Verilog HDL File  ; C:/cvs_sandbox/boards/stratix2_gx/stratix2_gx_pciex/pld/hello_gx/hello_gx_restored/hello_gx.v ;
+----------------------------------+-----------------+------------------------+-----------------------------------------------------------------------------------------------+


+--------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary            ;
+-----------------------------------------------+--------+
; Resource                                      ; Usage  ;
+-----------------------------------------------+--------+
; Estimated Total ALUTs                         ; 60     ;
; Total combinational functions                 ; 59     ;
; ALUT usage by number of inputs                ;        ;
;     -- 7 input functions                      ; 0      ;
;     -- 6 input functions                      ; 0      ;
;     -- 5 input functions                      ; 0      ;
;     -- 4 input functions                      ; 0      ;
;     -- <=3 input functions                    ; 59     ;
;         -- Combinational cells for routing    ; 0      ;
; ALUTs by mode                                 ;        ;
;     -- normal mode                            ; 11     ;
;     -- extended LUT mode                      ; 0      ;
;     -- arithmetic mode                        ; 48     ;
;     -- shared arithmetic mode                 ; 0      ;
; Total registers                               ; 50     ;
; Estimated ALMs:  partially or completely used ; 30     ;
; I/O pins                                      ; 32     ;
; Maximum fan-out node                          ; clk1_p ;
; Maximum fan-out                               ; 25     ;
; Total fan-out                                 ; 244    ;
; Average fan-out                               ; 1.73   ;
+-----------------------------------------------+--------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                              ;
+----------------------------+-------------------+--------------+-------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+---------------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; M512s ; M4Ks ; M-RAMs ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; Full Hierarchy Name ;
+----------------------------+-------------------+--------------+-------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+---------------------+
; |hello_gx                  ; 59 (59)           ; 50 (50)      ; 0           ; 0     ; 0    ; 0      ; 0            ; 0       ; 0         ; 0         ; 32   ; 0            ; |hello_gx           ;
+----------------------------+-------------------+--------------+-------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 50    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis INI Usage                                                                                          ;
+----------------------+--------------------------------------------------------------------------------------------------+
; Option               ; Usage                                                                                            ;
+----------------------+--------------------------------------------------------------------------------------------------+
; Initialization file: ; C:/cvs_sandbox/boards/stratix2_gx/stratix2_gx_pciex/pld/hello_gx/hello_gx_restored/quartus.ini   ;
; dev_password1        ; e502b9b5b8331ab9229c9cf94c8843892198e2e5f8f72615110014242253352313231725211522142056532342015155 ;
+----------------------+--------------------------------------------------------------------------------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Fri Jun 16 09:50:55 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off hello_gx -c hello_gx
Info: Found 1 design units, including 1 entities, in source file hello_gx.v
    Info: Found entity 1: hello_gx
Info: Elaborating entity "hello_gx" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at hello_gx.v(58): truncated value with size 32 to match size of target (25)
Warning (10230): Verilog HDL assignment warning at hello_gx.v(67): truncated value with size 32 to match size of target (25)
Info: Implemented 91 device resources after synthesis - the final resource count might be different
    Info: Implemented 13 input pins
    Info: Implemented 19 output pins
    Info: Implemented 59 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings
    Info: Processing ended: Fri Jun 16 09:50:59 2006
    Info: Elapsed time: 00:00:05