📄 ddr2_cpu.ptf
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radix = "hexadecimal";
}
SIGNAL abn
{
format = "Logic";
name = "W_valid";
radix = "hexadecimal";
}
SIGNAL abo
{
format = "Logic";
name = "W_wr_dst_reg";
radix = "hexadecimal";
}
SIGNAL abp
{
format = "Logic";
name = "W_dst_regnum";
radix = "hexadecimal";
}
SIGNAL abq
{
format = "Logic";
name = "W_wr_data";
radix = "hexadecimal";
}
SIGNAL abr
{
format = "Logic";
name = "F_en";
radix = "hexadecimal";
}
SIGNAL abs
{
format = "Logic";
name = "D_en";
radix = "hexadecimal";
}
SIGNAL abt
{
format = "Logic";
name = "E_en";
radix = "hexadecimal";
}
SIGNAL abu
{
format = "Logic";
name = "M_en";
radix = "hexadecimal";
}
SIGNAL abv
{
format = "Logic";
name = "F_iw";
radix = "hexadecimal";
}
SIGNAL abw
{
format = "Logic";
name = "D_iw";
radix = "hexadecimal";
}
SIGNAL abx
{
format = "Logic";
name = "E_iw";
radix = "hexadecimal";
}
SIGNAL aby
{
format = "Logic";
name = "E_valid_prior_to_hbreak";
radix = "hexadecimal";
}
SIGNAL abz
{
format = "Logic";
name = "M_pipe_flush_nxt";
radix = "hexadecimal";
}
SIGNAL aca
{
format = "Logic";
name = "M_pipe_flush_baddr_nxt";
radix = "hexadecimal";
}
SIGNAL acb
{
format = "Logic";
name = "M_status_reg_pie";
radix = "hexadecimal";
}
SIGNAL acc
{
format = "Logic";
name = "M_ienable_reg";
radix = "hexadecimal";
}
SIGNAL acd
{
format = "Logic";
name = "intr_req";
radix = "hexadecimal";
}
}
}
}
MODULE jtag_uart_0
{
class = "altera_avalon_jtag_uart";
class_version = "6.0";
iss_model_name = "altera_avalon_jtag_uart";
SLAVE avalon_jtag_slave
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Is_Printable_Device = "1";
Address_Alignment = "native";
Address_Width = "1";
Data_Width = "32";
Has_IRQ = "1";
Read_Wait_States = "peripheral_controlled";
Write_Wait_States = "peripheral_controlled";
JTAG_Hub_Base_Id = "0x04006E";
JTAG_Hub_Instance_Id = "0";
Connection_Limit = "1";
MASTERED_BY cpu_0/data_master
{
priority = "1";
}
IRQ_MASTER cpu_0/data_master
{
IRQ_Number = "0";
}
Base_Address = "0x00020860";
Address_Group = "0";
}
PORT_WIRING
{
PORT clk
{
type = "clk";
direction = "input";
width = "1";
Is_Enabled = "1";
}
PORT rst_n
{
type = "reset_n";
direction = "input";
width = "1";
Is_Enabled = "1";
}
PORT av_chipselect
{
type = "chipselect";
direction = "input";
width = "1";
Is_Enabled = "1";
}
PORT av_address
{
type = "address";
direction = "input";
width = "1";
Is_Enabled = "1";
}
PORT av_read_n
{
type = "read_n";
direction = "input";
width = "1";
Is_Enabled = "1";
}
PORT av_readdata
{
type = "readdata";
direction = "output";
width = "32";
Is_Enabled = "1";
}
PORT av_write_n
{
type = "write_n";
direction = "input";
width = "1";
Is_Enabled = "1";
}
PORT av_writedata
{
type = "writedata";
direction = "input";
width = "32";
Is_Enabled = "1";
}
PORT av_waitrequest
{
type = "waitrequest";
direction = "output";
width = "1";
Is_Enabled = "1";
}
PORT av_irq
{
type = "irq";
direction = "output";
width = "1";
Is_Enabled = "1";
}
PORT dataavailable
{
Is_Enabled = "1";
direction = "output";
type = "dataavailable";
width = "1";
}
PORT readyfordata
{
Is_Enabled = "1";
direction = "output";
type = "readyfordata";
width = "1";
}
}
}
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "1";
Is_Enabled = "1";
Iss_Launch_Telnet = "0";
Top_Level_Ports_Are_Enumerated = "1";
Clock_Source = "clk";
View
{
Settings_Summary = "<br>Write Depth: 64; Write IRQ Threshold: 8 <br>Read Depth: 64; Read IRQ Threshold: 8";
MESSAGES
{
}
Is_Collapsed = "1";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
write_depth = "64";
read_depth = "64";
write_threshold = "8";
read_threshold = "8";
read_char_stream = "";
showascii = "1";
read_le = "0";
write_le = "0";
altera_show_unreleased_jtag_uart_features = "0";
}
SIMULATION
{
Fix_Me_Up = "";
DISPLAY
{
SIGNAL av_chipselect
{
name = "av_chipselect";
}
SIGNAL av_address
{
name = "av_address";
radix = "hexadecimal";
}
SIGNAL av_read_n
{
name = "av_read_n";
}
SIGNAL av_readdata
{
name = "av_readdata";
radix = "hexadecimal";
}
SIGNAL av_write_n
{
name = "av_write_n";
}
SIGNAL av_writedata
{
name = "av_writedata";
radix = "hexadecimal";
}
SIGNAL av_waitrequest
{
name = "av_waitrequest";
}
SIGNAL av_irq
{
name = "av_irq";
}
SIGNAL dataavailable
{
name = "dataavailable";
}
SIGNAL readyfordata
{
name = "readyfordata";
}
}
INTERACTIVE_IN drive
{
enable = "0";
file = "_input_data_stream.dat";
mutex = "_input_data_mutex.dat";
log = "_in.log";
rate = "100";
signals = "temp,list";
exe = "nios2-terminal";
}
INTERACTIVE_OUT log
{
enable = "1";
exe = "perl -- atail-f.pl";
file = "_output_stream.dat";
radix = "ascii";
signals = "temp,list";
}
}
HDL_INFO
{
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/jtag_uart_0.vhd";
Synthesis_Only_Files = "";
}
PORT_WIRING
{
}
}
MODULE onchip_memory_0
{
class = "altera_avalon_onchip_memory2";
class_version = "6.0";
iss_model_name = "altera_memory";
HDL_INFO
{
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/onchip_memory_0.vhd";
Synthesis_Only_Files = "";
}
WIZARD_SCRIPT_ARGUMENTS
{
allow_mram_sim_contents_only_file = "0";
ram_block_type = "M-RAM";
init_contents_file = "onchip_memory_0";
non_default_init_file_enabled = "0";
gui_ram_block_type = "Automatic";
Writeable = "1";
dual_port = "0";
Size_Value = "128";
Size_Multiple = "1024";
MAKE
{
TARGET delete_placeholder_warning
{
onchip_memory_0
{
Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt";
Is_Phony = "1";
Target_File = "do_delete_placeholder_warning";
}
}
TARGET hex
{
onchip_memory_0
{
Command1 = "@echo Post-processing to create $(notdir $@)";
Command2 = "elf2hex $(ELF) 0x00000000 0x1FFFF --width=32 $(QUARTUS_PROJECT_DIR)/onchip_memory_0.hex --create-lanes=0 ";
Dependency = "$(ELF)";
Target_File = "$(QUARTUS_PROJECT_DIR)/onchip_memory_0.hex";
}
}
TARGET sim
{
onchip_memory_0
{
Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";
Command2 = "@echo Hardware simulation is not enabled for the target SOPC Builder system. Skipping creation of hardware simulation model contents and simulation symbol files. \\(Note: This does not affect the instruction set simulator.\\)";
Command3 = "touch $(SIMDIR)/dummy_file";
Dependency = "$(ELF)";
Target_File = "$(SIMDIR)/dummy_file";
}
}
}
contents_info = "QUARTUS_PROJECT_DIR/onchip_memory_0.hex 1151100796 ";
}
SYSTEM_BUILDER_INFO
{
Prohibited_Device_Family = "MERCURY, APEX20K, APEX20KE, APEX20KC, APEXII, ACEX1K, FLEX10KE, EXCALIBUR_ARM, MAXII";
Instantiate_In_System_Module = "1";
Is_Enabled = "1";
Default_Module_Name = "onchip_memory";
Top_Level_Ports_Are_Enumerated = "1";
Clock_Source = "clk";
View
{
MESSAGES
{
}
Is_Collapsed = "1";
}
}
SLAVE s1
{
PORT_WIRING
{
PORT address
{
Is_Enabled = "1";
direction = "input";
type = "address";
width = "15";
}
PORT byteenable
{
Is_Enabled = "1";
direction = "input";
type = "byteenable";
width = "4";
}
PORT chipselect
{
Is_Enabled = "1";
direction = "input";
type = "chipselect";
width = "1";
}
PORT clk
{
Is_Enabled = "1";
direction = "input";
type = "clk";
width = "1";
}
PORT clken
{
Is_Enabled = "1";
default_value = "1'b1";
direction = "input";
type = "clken";
width = "1";
}
PORT readdata
{
Is_Enabled = "1";
direction = "output";
type = "readdata";
width = "32";
}
PORT write
{
Is_Enabled = "1";
direction = "input";
type = "write";
width = "1";
}
PORT writedata
{
Is_Enabled = "1";
direction = "input";
type = "writedata";
width = "32";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Is_Memory_Device = "1";
Address_Group = "0";
Address_Alignment = "dynamic";
Address_Width = "15";
Data_Width = "32";
Has_IRQ = "0";
Read_Wait_States = "0";
Write_Wait_States = "0";
Address_Span = "131072";
Read_Latency = "1";
Is_Channel = "1";
Is_Writable = "1";
MASTERED_BY cpu_0/instruction_master
{
priority = "1";
}
MASTERED_BY cpu_0/data_master
{
priority = "1";
}
Base_Address = "0x00000000";
IRQ_MASTER cpu_0/data_master
{
IRQ_Number = "NC";
}
}
}
SLAVE s2
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Is_Memory_Device = "1";
Address_Group = "0";
Address_Alignment = "dynamic";
Address_Width = "15";
Data_Width = "32";
Has_IRQ = "0";
Read_Wait_States = "0";
Write_Wait_States = "0";
Address_Span = "131072";
Read_Latency = "1";
Is_Channel = "1";
Is_Enabled = "0";
Is_Writable = "1";
}
}
SIMULATION
{
DISPLAY
{
SIGNAL a
{
name = "chipselect";
conditional = "1";
}
SIGNAL b
{
name = "write";
conditional = "1";
}
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