ddr2_topecc_extraction_data.txt
来自「基于SIIGX的PCIe的Kit」· 文本 代码 · 共 1,910 行 · 第 1/5 页
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1,910 行
dqspin_2_dqsclk 1452
reg_2_post 713
post_2_dqsclk 112
dqsclk_2_post 413
array_name= min_paths_for_each_half_dq_115
dq_2_ddio 1153
ddio_2_core 557
core_2_reg 97
clk_2_pin 852
dqsclk_2_ddio_resync 413
dqspin_2_dqsclk 1452
reg_2_post 713
post_2_dqsclk 112
dqsclk_2_post 413
array_name= min_paths_for_each_half_dq_116
dq_2_ddio 1143
ddio_2_core 449
core_2_reg 97
clk_2_pin 852
dqsclk_2_ddio_resync 413
dqspin_2_dqsclk 1452
reg_2_post 713
post_2_dqsclk 112
dqsclk_2_post 413
array_name= min_paths_for_each_half_dq_117
dq_2_ddio 1153
ddio_2_core 461
core_2_reg 97
clk_2_pin 852
dqsclk_2_ddio_resync 413
dqspin_2_dqsclk 1452
reg_2_post 713
post_2_dqsclk 112
dqsclk_2_post 413
array_name= min_paths_for_each_half_dq_118
dq_2_ddio 1143
ddio_2_core 373
core_2_reg 97
clk_2_pin 852
dqsclk_2_ddio_resync 413
dqspin_2_dqsclk 1452
reg_2_post 713
post_2_dqsclk 112
dqsclk_2_post 413
array_name= min_paths_for_each_half_dq_119
dq_2_ddio 1153
ddio_2_core 466
core_2_reg 97
clk_2_pin 852
dqsclk_2_ddio_resync 413
dqspin_2_dqsclk 1452
reg_2_post 713
post_2_dqsclk 112
dqsclk_2_post 413
array_name= min_paths_for_each_half_dq_120
dq_2_ddio 1143
ddio_2_core 380
core_2_reg 97
clk_2_pin 852
dqsclk_2_ddio_resync 413
dqspin_2_dqsclk 1452
reg_2_post 713
post_2_dqsclk 112
dqsclk_2_post 413
array_name= min_paths_for_each_half_dq_121
dq_2_ddio 1153
ddio_2_core 397
core_2_reg 97
clk_2_pin 852
dqsclk_2_ddio_resync 413
dqspin_2_dqsclk 1452
reg_2_post 713
post_2_dqsclk 112
dqsclk_2_post 413
array_name= min_paths_for_each_half_dq_122
dq_2_ddio 1143
ddio_2_core 373
core_2_reg 97
clk_2_pin 852
dqsclk_2_ddio_resync 413
dqspin_2_dqsclk 1452
reg_2_post 713
post_2_dqsclk 112
dqsclk_2_post 413
array_name= min_paths_for_each_half_dq_123
dq_2_ddio 1153
ddio_2_core 476
core_2_reg 97
clk_2_pin 852
dqsclk_2_ddio_resync 413
dqspin_2_dqsclk 1452
reg_2_post 713
post_2_dqsclk 112
dqsclk_2_post 413
array_name= min_paths_for_each_half_dq_124
dq_2_ddio 1143
ddio_2_core 466
core_2_reg 97
clk_2_pin 852
dqsclk_2_ddio_resync 413
dqspin_2_dqsclk 1452
reg_2_post 713
post_2_dqsclk 112
dqsclk_2_post 413
array_name= min_paths_for_each_half_dq_125
dq_2_ddio 1153
ddio_2_core 470
core_2_reg 97
clk_2_pin 852
dqsclk_2_ddio_resync 413
dqspin_2_dqsclk 1452
reg_2_post 713
post_2_dqsclk 112
dqsclk_2_post 413
array_name= min_paths_for_each_half_dq_126
dq_2_ddio 1143
ddio_2_core 544
core_2_reg 97
clk_2_pin 852
dqsclk_2_ddio_resync 413
dqspin_2_dqsclk 1452
reg_2_post 713
post_2_dqsclk 112
dqsclk_2_post 413
array_name= min_paths_for_each_half_dq_127
dq_2_ddio 1153
ddio_2_core 472
core_2_reg 97
clk_2_pin 852
dqsclk_2_ddio_resync 413
dqspin_2_dqsclk 1452
reg_2_post 713
post_2_dqsclk 112
dqsclk_2_post 413
array_name= min_paths_for_each_half_dq_128
dq_2_ddio 1143
ddio_2_core 596
core_2_reg 97
clk_2_pin 852
dqsclk_2_ddio_resync 413
dqspin_2_dqsclk 1452
reg_2_post 734
post_2_dqsclk 112
dqsclk_2_post 413
array_name= min_paths_for_each_half_dq_129
dq_2_ddio 1153
ddio_2_core 488
core_2_reg 97
clk_2_pin 852
dqsclk_2_ddio_resync 413
dqspin_2_dqsclk 1452
reg_2_post 734
post_2_dqsclk 112
dqsclk_2_post 413
array_name= min_paths_for_each_half_dq_130
dq_2_ddio 1143
ddio_2_core 588
core_2_reg 97
clk_2_pin 852
dqsclk_2_ddio_resync 413
dqspin_2_dqsclk 1452
reg_2_post 734
post_2_dqsclk 112
dqsclk_2_post 413
array_name= min_paths_for_each_half_dq_131
dq_2_ddio 1153
ddio_2_core 493
core_2_reg 97
clk_2_pin 852
dqsclk_2_ddio_resync 413
dqspin_2_dqsclk 1452
reg_2_post 734
post_2_dqsclk 112
dqsclk_2_post 413
array_name= min_paths_for_each_half_dq_132
dq_2_ddio 1143
ddio_2_core 450
core_2_reg 97
clk_2_pin 852
dqsclk_2_ddio_resync 413
dqspin_2_dqsclk 1452
reg_2_post 734
post_2_dqsclk 112
dqsclk_2_post 413
array_name= min_paths_for_each_half_dq_133
dq_2_ddio 1153
ddio_2_core 519
core_2_reg 97
clk_2_pin 852
dqsclk_2_ddio_resync 413
dqspin_2_dqsclk 1452
reg_2_post 734
post_2_dqsclk 112
dqsclk_2_post 413
array_name= min_paths_for_each_half_dq_134
dq_2_ddio 1143
ddio_2_core 369
core_2_reg 97
clk_2_pin 852
dqsclk_2_ddio_resync 413
dqspin_2_dqsclk 1452
reg_2_post 734
post_2_dqsclk 112
dqsclk_2_post 413
array_name= min_paths_for_each_half_dq_135
dq_2_ddio 1153
ddio_2_core 474
core_2_reg 97
clk_2_pin 852
dqsclk_2_ddio_resync 413
dqspin_2_dqsclk 1452
reg_2_post 734
post_2_dqsclk 112
dqsclk_2_post 413
array_name= min_paths_for_each_half_dq_136
dq_2_ddio 1143
ddio_2_core 378
core_2_reg 97
clk_2_pin 852
dqsclk_2_ddio_resync 413
dqspin_2_dqsclk 1452
reg_2_post 734
post_2_dqsclk 112
dqsclk_2_post 413
array_name= min_paths_for_each_half_dq_137
dq_2_ddio 1153
ddio_2_core 397
core_2_reg 97
clk_2_pin 852
dqsclk_2_ddio_resync 413
dqspin_2_dqsclk 1452
reg_2_post 734
post_2_dqsclk 112
dqsclk_2_post 413
array_name= min_paths_for_each_half_dq_138
dq_2_ddio 1143
ddio_2_core 369
core_2_reg 97
clk_2_pin 852
dqsclk_2_ddio_resync 413
dqspin_2_dqsclk 1452
reg_2_post 734
post_2_dqsclk 112
dqsclk_2_post 413
array_name= min_paths_for_each_half_dq_139
dq_2_ddio 1153
ddio_2_core 480
core_2_reg 97
clk_2_pin 852
dqsclk_2_ddio_resync 413
dqspin_2_dqsclk 1452
reg_2_post 734
post_2_dqsclk 112
dqsclk_2_post 413
array_name= min_paths_for_each_half_dq_140
dq_2_ddio 1143
ddio_2_core 462
core_2_reg 97
clk_2_pin 852
dqsclk_2_ddio_resync 413
dqspin_2_dqsclk 1452
reg_2_post 734
post_2_dqsclk 112
dqsclk_2_post 413
array_name= min_paths_for_each_half_dq_141
dq_2_ddio 1153
ddio_2_core 468
core_2_reg 97
clk_2_pin 852
dqsclk_2_ddio_resync 413
dqspin_2_dqsclk 1452
reg_2_post 734
post_2_dqsclk 112
dqsclk_2_post 413
array_name= min_paths_for_each_half_dq_142
dq_2_ddio 1143
ddio_2_core 475
core_2_reg 97
clk_2_pin 852
dqsclk_2_ddio_resync 413
dqspin_2_dqsclk 1452
reg_2_post 734
post_2_dqsclk 112
dqsclk_2_post 413
array_name= min_paths_for_each_half_dq_143
dq_2_ddio 1153
ddio_2_core 572
core_2_reg 97
clk_2_pin 852
dqsclk_2_ddio_resync 413
dqspin_2_dqsclk 1452
reg_2_post 734
post_2_dqsclk 112
dqsclk_2_post 413
array_name= max_paths_for_each_half_dq_0
dq_2_ddio 1728
ddio_2_core 1133
core_2_reg 155
clk_2_pin 1423
dqsclk_2_ddio_resync 649
dqspin_2_dqsclk 1798
reg_2_post 1369
post_2_dqsclk 164
dqsclk_2_post 649
array_name= max_paths_for_each_half_dq_1
dq_2_ddio 1738
ddio_2_core 1152
core_2_reg 155
clk_2_pin 1423
dqsclk_2_ddio_resync 649
dqspin_2_dqsclk 1798
reg_2_post 1369
post_2_dqsclk 164
dqsclk_2_post 649
array_name= max_paths_for_each_half_dq_2
dq_2_ddio 1728
ddio_2_core 1118
core_2_reg 155
clk_2_pin 1423
dqsclk_2_ddio_resync 649
dqspin_2_dqsclk 1798
reg_2_post 1369
post_2_dqsclk 164
dqsclk_2_post 649
array_name= max_paths_for_each_half_dq_3
dq_2_ddio 1738
ddio_2_core 1125
core_2_reg 155
clk_2_pin 1423
dqsclk_2_ddio_resync 649
dqspin_2_dqsclk 1798
reg_2_post 1369
post_2_dqsclk 164
dqsclk_2_post 649
array_name= max_paths_for_each_half_dq_4
dq_2_ddio 1728
ddio_2_core 919
core_2_reg 155
clk_2_pin 1423
dqsclk_2_ddio_resync 649
dqspin_2_dqsclk 1798
reg_2_post 1369
post_2_dqsclk 164
dqsclk_2_post 649
array_name= max_paths_for_each_half_dq_5
dq_2_ddio 1738
ddio_2_core 927
core_2_reg 155
clk_2_pin 1423
dqsclk_2_ddio_resync 649
dqspin_2_dqsclk 1798
reg_2_post 1369
post_2_dqsclk 164
dqsclk_2_post 649
array_name= max_paths_for_each_half_dq_6
dq_2_ddio 1728
ddio_2_core 709
core_2_reg 155
clk_2_pin 1423
dqsclk_2_ddio_resync 649
dqspin_2_dqsclk 1798
reg_2_post 1369
post_2_dqsclk 164
dqsclk_2_post 649
array_name= max_paths_for_each_half_dq_7
dq_2_ddio 1738
ddio_2_core 935
core_2_reg 155
clk_2_pin 1423
dqsclk_2_ddio_resync 649
dqspin_2_dqsclk 1798
reg_2_post 1369
post_2_dqsclk 164
dqsclk_2_post 649
array_name= max_paths_for_each_half_dq_8
dq_2_ddio 1728
ddio_2_core 739
core_2_reg 155
clk_2_pin 1423
dqsclk_2_ddio_resync 649
dqspin_2_dqsclk 1798
reg_2_post 1369
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