ddr2_topecc_bb.v

基于SIIGX的PCIe的Kit

// Generated by DDR2 SDRAM Controller 3.4.0 [Altera, IP Toolbench v1.2.11 build48]
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2006 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera.  Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
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// the intellectual property, including patents, copyrights, trademarks,
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// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
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module ddr2_topecc (
	resynch_clk,
	addrcmd_clk,
	write_clk,
	clk,
	reset_n,
	local_read_req,
	local_write_req,
	local_addr,
	local_wdata,
	local_be,
	local_size,
	dqs_delay_ctrl,
	dqsupdate,
	local_ready,
	local_rdata,
	local_rdata_valid,
	local_rdvalid_in_n,
	local_init_done,
	local_refresh_ack,
	local_wdata_req,
	ddr2_odt,
	clk_to_sdram,
	clk_to_sdram_n,
	ddr2_cs_n,
	ddr2_cke,
	ddr2_a,
	ddr2_ba,
	ddr2_ras_n,
	ddr2_cas_n,
	ddr2_we_n,
	ddr2_dm,
	stratix_dll_control,
	ddr2_dq,
	ddr2_dqs);

	input		resynch_clk;
	input		addrcmd_clk;
	input		write_clk;
	input		clk;
	input		reset_n;
	input		local_read_req;
	input		local_write_req;
	input	[23:0]	local_addr;
	input	[143:0]	local_wdata;
	input	[17:0]	local_be;
	input	[1:0]	local_size;
	input	[5:0]	dqs_delay_ctrl;
	input		dqsupdate;
	output		local_ready;
	output	[143:0]	local_rdata;
	output		local_rdata_valid;
	output		local_rdvalid_in_n;
	output		local_init_done;
	output		local_refresh_ack;
	output		local_wdata_req;
	output		ddr2_odt;
	output	[2:0]	clk_to_sdram;
	output	[2:0]	clk_to_sdram_n;
	output		ddr2_cs_n;
	output		ddr2_cke;
	output	[12:0]	ddr2_a;
	output	[1:0]	ddr2_ba;
	output		ddr2_ras_n;
	output		ddr2_cas_n;
	output		ddr2_we_n;
	output	[8:0]	ddr2_dm;
	output		stratix_dll_control;
	inout	[71:0]	ddr2_dq;
	inout	[8:0]	ddr2_dqs;
endmodule