scfifo_a691.tdf

基于SIIGX的PCIe的Kit

--scfifo ADD_RAM_OUTPUT_REGISTER="ON" ALLOW_RWCYCLE_WHEN_FULL="OFF" ALMOST_EMPTY_VALUE=0 ALMOST_FULL_VALUE=8 DEVICE_FAMILY="Stratix II GX" LPM_NUMWORDS=16 LPM_SHOWAHEAD="OFF" lpm_width=162 lpm_widthu=4 OPTIMIZE_FOR_SPEED=5 OVERFLOW_CHECKING="OFF" UNDERFLOW_CHECKING="ON" USE_EAB="ON" aclr almost_full clock data q rdreq wrreq CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CYCLONEII_M4K_COMPATIBILITY="ON" LOW_POWER_MODE="AUTO" lpm_hint="USE_EAB=ON"
--VERSION_BEGIN 6.0 cbx_altdpram 2006:01:09:10:52:42:SJ cbx_altsyncram 2006:03:30:14:59:04:SJ cbx_cycloneii 2006:02:07:15:19:20:SJ cbx_fifo_common 2006:01:09:11:23:34:SJ cbx_lpm_add_sub 2006:01:09:11:17:20:SJ cbx_lpm_compare 2006:01:09:11:15:40:SJ cbx_lpm_counter 2006:03:23:14:19:24:SJ cbx_lpm_decode 2006:01:09:11:16:44:SJ cbx_lpm_mux 2006:01:09:11:16:16:SJ cbx_mgl 2006:04:14:11:14:36:SJ cbx_scfifo 2006:01:09:11:24:10:SJ cbx_stratix 2006:02:07:15:17:04:SJ cbx_stratixii 2006:03:03:09:35:36:SJ cbx_util_mgl 2006:01:09:10:46:36:SJ  VERSION_END


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FUNCTION a_dpfifo_7u11 (aclr, clock, data[161..0], rreq, sclr, wreq)
RETURNS ( q[161..0], usedw[3..0]);

--synthesis_resources = lut 15 ram_bits (auto) 2592 reg 22 
SUBDESIGN scfifo_a691
( 
	aclr	:	input;
	almost_full	:	output;
	clock	:	input;
	data[161..0]	:	input;
	q[161..0]	:	output;
	rdreq	:	input;
	wrreq	:	input;
) 
VARIABLE 
	dpfifo : a_dpfifo_7u11;
	dffe_af : dffe;
	comparison_af0	: WIRE;
	comparison_af1	: WIRE;
	comparison_af2	: WIRE;
	comparison_af3	: WIRE;
	comparison_pre_af0	: WIRE;
	comparison_pre_af1	: WIRE;
	comparison_pre_af2	: WIRE;
	comparison_pre_af3	: WIRE;
	sclr	: NODE;
	wire_af[3..0]	: WIRE;
	wire_pre_af[3..0]	: WIRE;

BEGIN 
	dpfifo.aclr = aclr;
	dpfifo.clock = clock;
	dpfifo.data[] = data[];
	dpfifo.rreq = rdreq;
	dpfifo.sclr = sclr;
	dpfifo.wreq = wrreq;
	dffe_af.CLK = clock;
	dffe_af.CLRN = (! aclr);
	dffe_af.D = ((dffe_af.Q & (dffe_af.Q $ (sclr # ((comparison_af3 & (! wrreq)) & rdreq)))) # ((! dffe_af.Q) & ((((! sclr) & comparison_pre_af3) & wrreq) & (! rdreq))));
	almost_full = dffe_af.Q;
	comparison_af0 = (dpfifo.usedw[0..0] $ wire_af[0..0]);
	comparison_af1 = ((dpfifo.usedw[1..1] $ wire_af[1..1]) & comparison_af0);
	comparison_af2 = ((dpfifo.usedw[2..2] $ wire_af[2..2]) & comparison_af1);
	comparison_af3 = ((dpfifo.usedw[3..3] $ wire_af[3..3]) & comparison_af2);
	comparison_pre_af0 = (dpfifo.usedw[0..0] $ wire_pre_af[0..0]);
	comparison_pre_af1 = ((dpfifo.usedw[1..1] $ wire_pre_af[1..1]) & comparison_pre_af0);
	comparison_pre_af2 = ((dpfifo.usedw[2..2] $ wire_pre_af[2..2]) & comparison_pre_af1);
	comparison_pre_af3 = ((dpfifo.usedw[3..3] $ wire_pre_af[3..3]) & comparison_pre_af2);
	q[] = dpfifo.q[];
	sclr = GND;
	wire_af[] = ( B"0", B"1", B"1", B"1");
	wire_pre_af[] = ( B"1", B"0", B"0", B"0");
END;
--VALID FILE