mult_add_nu72.tdf

基于SIIGX的PCIe的Kit

--altmult_add ADDNSUB_MULTIPLIER_REGISTER1="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEDICATED_MULTIPLIER_CIRCUITRY="YES" DEVICE_FAMILY="Stratix II GX" DSP_BLOCK_BALANCING="Auto" INPUT_ACLR_A0="ACLR0" INPUT_ACLR_B0="ACLR0" INPUT_REGISTER_A0="CLOCK0" INPUT_REGISTER_B0="CLOCK0" INPUT_SOURCE_A0="DATAA" INPUT_SOURCE_B0="DATAB" MULTIPLIER1_DIRECTION="ADD" MULTIPLIER_REGISTER0="UNREGISTERED" NUMBER_OF_MULTIPLIERS=1 OUTPUT_ACLR="ACLR1" OUTPUT_REGISTER="CLOCK1" SIGNED_ACLR_A="ACLR0" SIGNED_ACLR_B="ACLR0" SIGNED_PIPELINE_REGISTER_A="UNREGISTERED" SIGNED_PIPELINE_REGISTER_B="UNREGISTERED" SIGNED_REGISTER_A="CLOCK0" SIGNED_REGISTER_B="CLOCK0" WIDTH_A=32 WIDTH_B=32 WIDTH_RESULT=64 aclr0 aclr1 clock0 clock1 dataa datab result signa signb CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
--VERSION_BEGIN 6.0 cbx_alt_ded_mult_y 2006:01:23:16:19:44:SJ cbx_altmult_add 2006:04:03:10:38:52:SJ cbx_cycloneii 2006:02:07:15:19:20:SJ cbx_lpm_add_sub 2006:01:09:11:17:20:SJ cbx_mgl 2006:04:14:11:14:36:SJ cbx_padd 2006:01:12:17:31:50:SJ cbx_parallel_add 2006:02:24:16:50:46:SJ cbx_stratix 2006:02:07:15:17:04:SJ cbx_stratixii 2006:03:03:09:35:36:SJ cbx_util_mgl 2006:01:09:10:46:36:SJ  VERSION_END


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FUNCTION stratixiigx_mac_mult (aclr[3..0], clk[3..0], dataa[dataa_width-1..0], datab[datab_width-1..0], ena[3..0], mode, round, saturate, scanina[dataa_width-1..0], scaninb[datab_width-1..0], signa, signb, sourcea, sourceb, zeroacc)
WITH ( 	bypass_multiplier,	dataa_clear,	dataa_clock,	dataa_width,	datab_clear,	datab_clock,	datab_width,	mode_clear,	mode_clock,	output_clear,	output_clock,	round_clear,	round_clock,	saturate_clear,	saturate_clock,	signa_clear,	signa_clock,	signa_internally_grounded,	signb_clear,	signb_clock,	signb_internally_grounded,	zeroacc_clear,	zeroacc_clock) 
RETURNS ( dataout[dataa_width+datab_width-1..0], scanouta[dataa_width-1..0], scanoutb[datab_width-1..0]);
PARAMETERS
(
	dataa_width = 1,
	datab_width = 1,
	datac_width = 1,
	datad_width = 1,
	dataout_width = 144
);
FUNCTION stratixiigx_mac_out (aclr[3..0], addnsub0, addnsub1, clk[3..0], dataa[dataa_width-1..0], datab[datab_width-1..0], datac[datac_width-1..0], datad[datad_width-1..0], ena[3..0], mode0, mode1, multabsaturate, multcdsaturate, round0, round1, saturate, saturate1, signa, signb, zeroacc, zeroacc1)
WITH ( 	addnsub0_clear,	addnsub0_clock,	addnsub0_pipeline_clear,	addnsub0_pipeline_clock,	addnsub1_clear,	addnsub1_clock,	addnsub1_pipeline_clear,	addnsub1_pipeline_clock,	dataa_forced_to_zero,	dataa_width,	datab_width,	datac_forced_to_zero,	datac_width,	datad_width,	dataout_width,	mode0_clear,	mode0_clock,	mode0_pipeline_clear,	mode0_pipeline_clock,	mode1_clear,	mode1_clock,	mode1_pipeline_clear,	mode1_pipeline_clock,	multabsaturate_clear,	multabsaturate_clock,	multabsaturate_pipeline_clear,	multabsaturate_pipeline_clock,	multcdsaturate_clear,	multcdsaturate_clock,	multcdsaturate_pipeline_clear,	multcdsaturate_pipeline_clock,	operation_mode,	output1_clear,	output1_clock,	output2_clear,	output2_clock,	output3_clear,	output3_clock,	output4_clear,	output4_clock,	output5_clear,	output5_clock,	output6_clear,	output6_clock,	output7_clear,	output7_clock,	output_clear,	output_clock,	round0_clear,	round0_clock,	round0_pipeline_clear,	round0_pipeline_clock,	round1_clear,	round1_clock,	round1_pipeline_clear,	round1_pipeline_clock,	saturate1_clear,	saturate1_clock,	saturate1_pipeline_clear,	saturate1_pipeline_clock,	saturate_clear,	saturate_clock,	saturate_pipeline_clear,	saturate_pipeline_clock,	signa_clear,	signa_clock,	signa_pipeline_clear,	signa_pipeline_clock,	signb_clear,	signb_clock,	signb_pipeline_clear,	signb_pipeline_clock,	zeroacc1_clear,	zeroacc1_clock,	zeroacc1_pipeline_clear,	zeroacc1_pipeline_clock,	zeroacc_clear,	zeroacc_clock,	zeroacc_pipeline_clear,	zeroacc_pipeline_clock) 
RETURNS ( accoverflow, dataout[dataout_width-1..0]);

--synthesis_resources = dsp_9bit 8 
SUBDESIGN mult_add_nu72
( 
	aclr0	:	input;
	aclr1	:	input;
	clock0	:	input;
	clock1	:	input;
	dataa[31..0]	:	input;
	datab[31..0]	:	input;
	result[63..0]	:	output;
	signa	:	input;
	signb	:	input;
) 
VARIABLE 
	mac_mult1 : stratixiigx_mac_mult
		WITH (
			dataa_clear = "0",
			dataa_clock = "0",
			dataa_width = 18,
			datab_clear = "0",
			datab_clock = "0",
			datab_width = 18,
			signa_internally_grounded = "true",
			signb_internally_grounded = "true"
		);
	mac_mult2 : stratixiigx_mac_mult
		WITH (
			dataa_clear = "0",
			dataa_clock = "0",
			dataa_width = 18,
			datab_clear = "0",
			datab_clock = "0",
			datab_width = 18
		);
	mac_mult3 : stratixiigx_mac_mult
		WITH (
			dataa_clear = "0",
			dataa_clock = "0",
			dataa_width = 18,
			datab_clear = "0",
			datab_clock = "0",
			datab_width = 18,
			signb_internally_grounded = "true"
		);
	mac_mult4 : stratixiigx_mac_mult
		WITH (
			dataa_clear = "0",
			dataa_clock = "0",
			dataa_width = 18,
			datab_clear = "0",
			datab_clock = "0",
			datab_width = 18,
			signa_internally_grounded = "true"
		);
	mac_out5 : stratixiigx_mac_out
		WITH (
			dataa_width = 36,
			datab_width = 36,
			datac_width = 36,
			datad_width = 36,
			dataout_width = 144,
			operation_mode = "36_bit_multiply",
			output_clear = "1",
			output_clock = "1"
		);
	aclr2	: NODE;
	aclr3	: NODE;
	clock2	: NODE;
	clock3	: NODE;
	ena0	: NODE;
	ena1	: NODE;
	ena2	: NODE;
	ena3	: NODE;
	w11w[32..0]	: WIRE;
	w15w[32..0]	: WIRE;
	w23w[32..0]	: WIRE;
	w25w[32..0]	: WIRE;
	w27w[32..0]	: WIRE;
	w31w[32..0]	: WIRE;
	w7w[32..0]	: WIRE;
	w9w[32..0]	: WIRE;

BEGIN 
	mac_mult1.aclr[] = ( aclr3, aclr2, aclr1, aclr0);
	mac_mult1.clk[] = ( clock3, clock2, clock1, clock0);
	mac_mult1.dataa[] = ( w11w[14..0], B"000");
	mac_mult1.datab[] = ( w27w[14..0], B"000");
	mac_mult1.ena[] = ( ena3, ena2, ena1, ena0);
	mac_mult1.signa = B"1";
	mac_mult1.signb = B"1";
	mac_mult2.aclr[] = ( aclr3, aclr2, aclr1, aclr0);
	mac_mult2.clk[] = ( clock3, clock2, clock1, clock0);
	mac_mult2.dataa[17..0] = w7w[32..15];
	mac_mult2.datab[17..0] = w23w[32..15];
	mac_mult2.ena[] = ( ena3, ena2, ena1, ena0);
	mac_mult2.signa = B"1";
	mac_mult2.signb = B"1";
	mac_mult3.aclr[] = ( aclr3, aclr2, aclr1, aclr0);
	mac_mult3.clk[] = ( clock3, clock2, clock1, clock0);
	mac_mult3.dataa[17..0] = w9w[32..15];
	mac_mult3.datab[] = ( w31w[14..0], B"000");
	mac_mult3.ena[] = ( ena3, ena2, ena1, ena0);
	mac_mult3.signa = B"1";
	mac_mult3.signb = B"1";
	mac_mult4.aclr[] = ( aclr3, aclr2, aclr1, aclr0);
	mac_mult4.clk[] = ( clock3, clock2, clock1, clock0);
	mac_mult4.dataa[] = ( w15w[14..0], B"000");
	mac_mult4.datab[17..0] = w25w[32..15];
	mac_mult4.ena[] = ( ena3, ena2, ena1, ena0);
	mac_mult4.signa = B"1";
	mac_mult4.signb = B"1";
	mac_out5.aclr[] = ( aclr3, aclr2, aclr1, aclr0);
	mac_out5.clk[] = ( clock3, clock2, clock1, clock0);
	mac_out5.dataa[] = mac_mult1.dataout[];
	mac_out5.datab[] = mac_mult2.dataout[];
	mac_out5.datac[] = mac_mult3.dataout[];
	mac_out5.datad[] = mac_mult4.dataout[];
	mac_out5.ena[] = ( ena3, ena2, ena1, ena0);
	mac_out5.signa = B"1";
	mac_out5.signb = B"1";
	aclr2 = GND;
	aclr3 = GND;
	clock2 = VCC;
	clock3 = VCC;
	ena0 = VCC;
	ena1 = VCC;
	ena2 = VCC;
	ena3 = VCC;
	result[63..0] = mac_out5.dataout[69..6];
	w11w[] = ( (signa & dataa[31..31]), dataa[]);
	w15w[] = ( (signa & dataa[31..31]), dataa[]);
	w23w[] = ( (signb & datab[31..31]), datab[]);
	w25w[] = ( (signb & datab[31..31]), datab[]);
	w27w[] = ( (signb & datab[31..31]), datab[]);
	w31w[] = ( (signb & datab[31..31]), datab[]);
	w7w[] = ( (signa & dataa[31..31]), dataa[]);
	w9w[] = ( (signa & dataa[31..31]), dataa[]);
END;
--VALID FILE