a_dpfifo_7u11.tdf

基于SIIGX的PCIe的Kit

--a_dpfifo ADD_RAM_OUTPUT_REGISTER="ON" ALLOW_RWCYCLE_WHEN_FULL="OFF" DEVICE_FAMILY="Stratix II GX" LPM_NUMWORDS=16 LPM_SHOWAHEAD="OFF" lpm_width=162 lpm_widthu=4 OVERFLOW_CHECKING="OFF" UNDERFLOW_CHECKING="ON" aclr clock data q rreq sclr usedw wreq CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CYCLONEII_M4K_COMPATIBILITY="ON" LOW_POWER_MODE="AUTO" lpm_hint="USE_EAB=ON"
--VERSION_BEGIN 6.0 cbx_altdpram 2006:01:09:10:52:42:SJ cbx_altsyncram 2006:03:30:14:59:04:SJ cbx_cycloneii 2006:02:07:15:19:20:SJ cbx_fifo_common 2006:01:09:11:23:34:SJ cbx_lpm_add_sub 2006:01:09:11:17:20:SJ cbx_lpm_compare 2006:01:09:11:15:40:SJ cbx_lpm_counter 2006:03:23:14:19:24:SJ cbx_lpm_decode 2006:01:09:11:16:44:SJ cbx_lpm_mux 2006:01:09:11:16:16:SJ cbx_mgl 2006:04:14:11:14:36:SJ cbx_scfifo 2006:01:09:11:24:10:SJ cbx_stratix 2006:02:07:15:17:04:SJ cbx_stratixii 2006:03:03:09:35:36:SJ cbx_util_mgl 2006:01:09:10:46:36:SJ  VERSION_END


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FUNCTION altsyncram_a6e1 (address_a[3..0], address_b[3..0], clock0, clock1, clocken1, data_a[161..0], wren_a)
RETURNS ( q_b[161..0]);
FUNCTION cntr_bu8 (aclr, clock, cnt_en, sclr)
RETURNS ( q[2..0]);
FUNCTION cntr_qs7 (aclr, clock, cnt_en, sclr, updown)
RETURNS ( q[3..0]);
FUNCTION cntr_cu8 (aclr, clock, cnt_en, sclr)
RETURNS ( q[3..0]);

--synthesis_resources = lut 15 ram_bits (auto) 2592 reg 21 
SUBDESIGN a_dpfifo_7u11
( 
	aclr	:	input;
	clock	:	input;
	data[161..0]	:	input;
	q[161..0]	:	output;
	rreq	:	input;
	sclr	:	input;
	usedw[3..0]	:	output;
	wreq	:	input;
) 
VARIABLE 
	FIFOram : altsyncram_a6e1;
	empty_dff : dffe;
	full_dff : dffe;
	low_addressa[3..0] : dffe;
	rd_ptr_lsb : dffe;
	usedw_is_0_dff : dffe;
	usedw_is_1_dff : dffe;
	wrreq_delay : dffe;
	almost_full_comparer_aeb_int	:	WIRE;
	almost_full_comparer_aeb	:	WIRE;
	almost_full_comparer_dataa[3..0]	:	WIRE;
	almost_full_comparer_datab[3..0]	:	WIRE;
	two_comparison_aeb_int	:	WIRE;
	two_comparison_aeb	:	WIRE;
	two_comparison_dataa[3..0]	:	WIRE;
	two_comparison_datab[3..0]	:	WIRE;
	rd_ptr_msb : cntr_bu8;
	usedw_counter : cntr_qs7;
	wr_ptr : cntr_cu8;
	asynch_read_counter_enable	: WIRE;
	empty_out	: WIRE;
	pulse_ram_output	: WIRE;
	ram_read_address[3..0]	: WIRE;
	rd_ptr[3..0]	: WIRE;
	usedw_is_0	: WIRE;
	usedw_is_1	: WIRE;
	usedw_is_2	: WIRE;
	usedw_will_be_0	: WIRE;
	usedw_will_be_1	: WIRE;
	valid_rreq	: WIRE;
	valid_wreq	: WIRE;
	wait_state	: WIRE;

BEGIN 
	FIFOram.address_a[] = wr_ptr.q[];
	FIFOram.address_b[] = ram_read_address[];
	FIFOram.clock0 = clock;
	FIFOram.clock1 = clock;
	FIFOram.clocken1 = pulse_ram_output;
	FIFOram.data_a[] = data[];
	FIFOram.wren_a = valid_wreq;
	empty_dff.CLK = clock;
	empty_dff.CLRN = (! aclr);
	empty_dff.D = ((! (usedw_will_be_0 # wait_state)) & (! sclr));
	full_dff.CLK = clock;
	full_dff.CLRN = (! aclr);
	full_dff.D = ((! sclr) & (((valid_wreq & (! valid_rreq)) & almost_full_comparer_aeb) # (full_dff.Q & (! (valid_wreq $ valid_rreq)))));
	low_addressa[].CLK = clock;
	low_addressa[].CLRN = (! aclr);
	low_addressa[].D = ((! sclr) & ((asynch_read_counter_enable & rd_ptr[]) # ((! asynch_read_counter_enable) & low_addressa[].Q)));
	rd_ptr_lsb.CLK = clock;
	rd_ptr_lsb.CLRN = (! aclr);
	rd_ptr_lsb.D = ((! rd_ptr_lsb.Q) & (! sclr));
	rd_ptr_lsb.ENA = (asynch_read_counter_enable # sclr);
	usedw_is_0_dff.CLK = clock;
	usedw_is_0_dff.CLRN = (! aclr);
	usedw_is_0_dff.D = (! usedw_will_be_0);
	usedw_is_1_dff.CLK = clock;
	usedw_is_1_dff.CLRN = (! aclr);
	usedw_is_1_dff.D = usedw_will_be_1;
	wrreq_delay.CLK = clock;
	wrreq_delay.CLRN = (! aclr);
	wrreq_delay.D = ((! sclr) & valid_wreq);
	IF (almost_full_comparer_dataa[] == almost_full_comparer_datab[]) THEN
		almost_full_comparer_aeb_int = VCC;
	ELSE
		almost_full_comparer_aeb_int = GND;
	END IF;
	almost_full_comparer_aeb = almost_full_comparer_aeb_int;
	almost_full_comparer_dataa[] = B"1111";
	almost_full_comparer_datab[] = usedw_counter.q[];
	IF (two_comparison_dataa[] == two_comparison_datab[]) THEN
		two_comparison_aeb_int = VCC;
	ELSE
		two_comparison_aeb_int = GND;
	END IF;
	two_comparison_aeb = two_comparison_aeb_int;
	two_comparison_dataa[] = usedw_counter.q[];
	two_comparison_datab[] = ( B"00", B"1", B"0");
	rd_ptr_msb.aclr = aclr;
	rd_ptr_msb.clock = clock;
	rd_ptr_msb.cnt_en = (asynch_read_counter_enable & (! rd_ptr_lsb.Q));
	rd_ptr_msb.sclr = sclr;
	usedw_counter.aclr = aclr;
	usedw_counter.clock = clock;
	usedw_counter.cnt_en = (valid_wreq $ valid_rreq);
	usedw_counter.sclr = sclr;
	usedw_counter.updown = valid_wreq;
	wr_ptr.aclr = aclr;
	wr_ptr.clock = clock;
	wr_ptr.cnt_en = valid_wreq;
	wr_ptr.sclr = sclr;
	asynch_read_counter_enable = pulse_ram_output;
	empty_out = (! empty_dff.Q);
	pulse_ram_output = valid_rreq;
	q[] = FIFOram.q_b[];
	ram_read_address[] = (((! asynch_read_counter_enable) & low_addressa[].Q) # (asynch_read_counter_enable & rd_ptr[]));
	rd_ptr[] = ( rd_ptr_msb.q[], (! rd_ptr_lsb.Q));
	usedw[] = usedw_counter.q[];
	usedw_is_0 = (! usedw_is_0_dff.Q);
	usedw_is_1 = usedw_is_1_dff.Q;
	usedw_is_2 = two_comparison_aeb;
	usedw_will_be_0 = (! ((! sclr) & (! (((usedw_is_1 & valid_rreq) & (! valid_wreq)) # (usedw_is_0 & (! (valid_wreq $ valid_rreq)))))));
	usedw_will_be_1 = ((! sclr) & ((((usedw_is_2 & (! valid_wreq)) & valid_rreq) # (usedw_is_1 & (! (valid_wreq $ valid_rreq)))) # ((usedw_is_0 & valid_wreq) & (! valid_rreq))));
	valid_rreq = (rreq & (! empty_out));
	valid_wreq = wreq;
	wait_state = (usedw_will_be_1 & valid_wreq);
END;
--VALID FILE