ddr2_topecc_auk_ddr_dqs_group.v

基于SIIGX的PCIe的Kit

      .delayctrlin (),
      .devclrn (),
      .devoe (),
      .devpor (),
      .dqsbusout (),
      .dqsupdateen (),
      .inclk (dq_capture_clk),
      .inclkena (1'b1),
      .linkin (),
      .linkout (),
      .oe (dq_oe),
      .offsetctrlin (),
      .outclk (write_clk),
      .outclkena (1'b1),
      .padio (ddr_dq[6]),
      .regout (dq_captured_falling[6]),
      .sreset (),
      .terminationcontrol ()
    );

  defparam \g_dq_io:6:dq_io .bus_hold = "false",
           \g_dq_io:6:dq_io .ddio_mode = "bidir",
           \g_dq_io:6:dq_io .ddioinclk_input = "negated_inclk",
           \g_dq_io:6:dq_io .dqs_ctrl_latches_enable = "false",
           \g_dq_io:6:dq_io .dqs_delay_buffer_mode = "none",
           \g_dq_io:6:dq_io .dqs_edge_detect_enable = "false",
           \g_dq_io:6:dq_io .dqs_input_frequency = "none",
           \g_dq_io:6:dq_io .dqs_offsetctrl_enable = "false",
           \g_dq_io:6:dq_io .dqs_out_mode = "none",
           \g_dq_io:6:dq_io .dqs_phase_shift = 0,
           \g_dq_io:6:dq_io .extend_oe_disable = "false",
           \g_dq_io:6:dq_io .gated_dqs = "false",
           \g_dq_io:6:dq_io .inclk_input = "dqs_bus",
           \g_dq_io:6:dq_io .input_async_reset = "clear",
           \g_dq_io:6:dq_io .input_power_up = "low",
           \g_dq_io:6:dq_io .input_register_mode = "register",
           \g_dq_io:6:dq_io .input_sync_reset = "none",
           \g_dq_io:6:dq_io .lpm_type = "stratixii_io",
           \g_dq_io:6:dq_io .oe_async_reset = "clear",
           \g_dq_io:6:dq_io .oe_power_up = "low",
           \g_dq_io:6:dq_io .oe_register_mode = "register",
           \g_dq_io:6:dq_io .oe_sync_reset = "none",
           \g_dq_io:6:dq_io .open_drain_output = "false",
           \g_dq_io:6:dq_io .operation_mode = "bidir",
           \g_dq_io:6:dq_io .output_async_reset = "clear",
           \g_dq_io:6:dq_io .output_power_up = "low",
           \g_dq_io:6:dq_io .output_register_mode = "register",
           \g_dq_io:6:dq_io .output_sync_reset = "none",
           \g_dq_io:6:dq_io .sim_dqs_delay_increment = 0,
           \g_dq_io:6:dq_io .sim_dqs_intrinsic_delay = 0,
           \g_dq_io:6:dq_io .sim_dqs_offset_increment = 0,
           \g_dq_io:6:dq_io .tie_off_oe_clock_enable = "false",
           \g_dq_io:6:dq_io .tie_off_output_clock_enable = "false";

  stratixii_io \g_dq_io:7:dq_io 
    (
      .areset (reset),
      .combout (),
      .datain (wdata_r[7]),
      .ddiodatain (wdata_r[15]),
      .ddioinclk (ZEROS[0]),
      .ddioregout (dq_captured_rising[7]),
      .delayctrlin (),
      .devclrn (),
      .devoe (),
      .devpor (),
      .dqsbusout (),
      .dqsupdateen (),
      .inclk (dq_capture_clk),
      .inclkena (1'b1),
      .linkin (),
      .linkout (),
      .oe (dq_oe),
      .offsetctrlin (),
      .outclk (write_clk),
      .outclkena (1'b1),
      .padio (ddr_dq[7]),
      .regout (dq_captured_falling[7]),
      .sreset (),
      .terminationcontrol ()
    );

  defparam \g_dq_io:7:dq_io .bus_hold = "false",
           \g_dq_io:7:dq_io .ddio_mode = "bidir",
           \g_dq_io:7:dq_io .ddioinclk_input = "negated_inclk",
           \g_dq_io:7:dq_io .dqs_ctrl_latches_enable = "false",
           \g_dq_io:7:dq_io .dqs_delay_buffer_mode = "none",
           \g_dq_io:7:dq_io .dqs_edge_detect_enable = "false",
           \g_dq_io:7:dq_io .dqs_input_frequency = "none",
           \g_dq_io:7:dq_io .dqs_offsetctrl_enable = "false",
           \g_dq_io:7:dq_io .dqs_out_mode = "none",
           \g_dq_io:7:dq_io .dqs_phase_shift = 0,
           \g_dq_io:7:dq_io .extend_oe_disable = "false",
           \g_dq_io:7:dq_io .gated_dqs = "false",
           \g_dq_io:7:dq_io .inclk_input = "dqs_bus",
           \g_dq_io:7:dq_io .input_async_reset = "clear",
           \g_dq_io:7:dq_io .input_power_up = "low",
           \g_dq_io:7:dq_io .input_register_mode = "register",
           \g_dq_io:7:dq_io .input_sync_reset = "none",
           \g_dq_io:7:dq_io .lpm_type = "stratixii_io",
           \g_dq_io:7:dq_io .oe_async_reset = "clear",
           \g_dq_io:7:dq_io .oe_power_up = "low",
           \g_dq_io:7:dq_io .oe_register_mode = "register",
           \g_dq_io:7:dq_io .oe_sync_reset = "none",
           \g_dq_io:7:dq_io .open_drain_output = "false",
           \g_dq_io:7:dq_io .operation_mode = "bidir",
           \g_dq_io:7:dq_io .output_async_reset = "clear",
           \g_dq_io:7:dq_io .output_power_up = "low",
           \g_dq_io:7:dq_io .output_register_mode = "register",
           \g_dq_io:7:dq_io .output_sync_reset = "none",
           \g_dq_io:7:dq_io .sim_dqs_delay_increment = 0,
           \g_dq_io:7:dq_io .sim_dqs_intrinsic_delay = 0,
           \g_dq_io:7:dq_io .sim_dqs_offset_increment = 0,
           \g_dq_io:7:dq_io .tie_off_oe_clock_enable = "false",
           \g_dq_io:7:dq_io .tie_off_output_clock_enable = "false";

  //-----------------------------------------------------------------------------
  //Write data registers
  //These are the last registers before the registers in the altddio_bidir. They
  //are clocked off the system clock but feed registers which are clocked off the
  //write clock, so their output is the beginning of 3/4 cycle path.
  //-----------------------------------------------------------------------------
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          wdata_r <= 0;
      else if (wdata_valid)
          //don't latch in data unless it's valid
          wdata_r <= wdata;

    end


  //Concatenate the rising and falling edge data to make a single bus
  assign dq_captured_0 = {dq_captured_falling, dq_captured_rising};

  assign #750 dq_captured_1 = dq_captured_0;
  assign #750 dq_captured_2 = dq_captured_1;
  assign #750 dq_captured_3 = dq_captured_2;
  assign #750 dq_captured_4 = dq_captured_3;
  assign #750 dq_captured_5 = dq_captured_4;
  //Apply delays in 6 chunks to avoid having to use transport delays
  assign #750 delayed_dq_captured = dq_captured_5;

  //-----------------------------------------------------------------------------
  //Resynchronisation registers
  //These registers resychronise the captured read data from the DQS clock
  //domain back into an internal PLL clock domain. 
  //-----------------------------------------------------------------------------
  //Use a rising edge for resynch
  always @(posedge resynch_clk or negedge reset_n)
    begin
      if (reset_n == 0)
          resynched_data <= 0;
      else 
        resynched_data <= delayed_dq_captured;
    end


  //-----------------------------------------------------------------------------
  //Post-resynch negedge registers
  //These optional registers can be inserted to make it easier to resynch between
  //the resynch clock and the system clock by optionally inserting a negedge
  //system clock register stage.
  //Note that the rdata_valid signal is also pipelined if this is set.
  //-----------------------------------------------------------------------------
  always @(negedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          inter_rdata <= 0;
      else 
        inter_rdata <= resynched_data;
    end


  //-----------------------------------------------------------------------------
  //Pipeline read data registers
  //These optional registers can be inserted to make it easier to meet timing
  //coming out of the local_rdata port of the core. It's especially necessary
  //if a falling edge resynch edge is being used..
  //Note that the rdata_valid signal is also pipelined if this is set.
  //-----------------------------------------------------------------------------

  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          rdata <= 0;
      else 
        rdata <= inter_rdata;
    end



//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  stratixii_io dqs_io
    (
      .areset (1'b1),
      .combout (undelayed_dqs),
      .datain (dqs_oe_r),
      .ddiodatain (ZEROS[0]),
      .ddioinclk (),
      .ddioregout (),
      .delayctrlin (dqs_delay_ctrl),
      .devclrn (),
      .devoe (),
      .devpor (),
      .dqsbusout (dqs_clk),
      .dqsupdateen (dqsupdate),
      .inclk (not_dqs_clk),
      .inclkena (1'b1),
      .linkin (),
      .linkout (),
      .oe (dqs_oe),
      .offsetctrlin (),
      .outclk (clk),
      .outclkena (1'b1),
      .padio (ddr_dqs),
      .regout (),
      .sreset (),
      .terminationcontrol ()
    );

  defparam dqs_io.bus_hold = "false",
           dqs_io.ddio_mode = "output",
           dqs_io.ddioinclk_input = "inclk",
           dqs_io.dqs_ctrl_latches_enable = "true",
           dqs_io.dqs_delay_buffer_mode = gSTRATIXII_DLL_DELAY_BUFFER_MODE,
           dqs_io.dqs_edge_detect_enable = "false",
           dqs_io.dqs_input_frequency = gDLL_INPUT_FREQUENCY,
           dqs_io.dqs_offsetctrl_enable = "false",
           dqs_io.dqs_out_mode = gSTRATIXII_DQS_OUT_MODE,
           dqs_io.dqs_phase_shift = 9000,
           dqs_io.extend_oe_disable = "true",
           dqs_io.gated_dqs = "true",
           dqs_io.inclk_input = "dqs_bus",
           dqs_io.input_async_reset = "preset",
           dqs_io.input_power_up = "high",
           dqs_io.input_register_mode = "register",
           dqs_io.input_sync_reset = "clear",
           dqs_io.lpm_type = "stratixii_io",
           dqs_io.oe_async_reset = "none",
           dqs_io.oe_power_up = "low",
           dqs_io.oe_register_mode = "register",
           dqs_io.oe_sync_reset = "none",
           dqs_io.open_drain_output = "false",
           dqs_io.operation_mode = "bidir",
           dqs_io.output_async_reset = "none",
           dqs_io.output_power_up = "low",
           dqs_io.output_register_mode = "register",
           dqs_io.output_sync_reset = "none",
           dqs_io.sim_dqs_delay_increment = 36,
           dqs_io.sim_dqs_intrinsic_delay = 900,
           dqs_io.sim_dqs_offset_increment = 0,
           dqs_io.tie_off_oe_clock_enable = "false",
           dqs_io.tie_off_output_clock_enable = "false";


//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on
//synthesis read_comments_as_HDL on
//  stratixii_io dqs_io
//    (
//      .areset (dq_enable_reset),
//      .combout (undelayed_dqs),
//      .datain (dqs_oe_r),
//      .ddiodatain (ZEROS[0]),
//      .ddioinclk (),
//      .ddioregout (),
//      .delayctrlin (dqs_delay_ctrl),
//      .devclrn (),
//      .devoe (),
//      .devpor (),
//      .dqsbusout (dqs_clk),
//      .dqsupdateen (dqsupdate),
//      .inclk (not_dqs_clk),
//      .inclkena (1'b1),
//      .linkin (),
//      .linkout (),
//      .oe (dqs_oe),
//      .offsetctrlin (),
//      .outclk (clk),
//      .outclkena (1'b1),
//      .padio (ddr_dqs),
//      .regout (),
//      .sreset (1'b1),
//      .terminationcontrol ()
//    );
//
//  defparam dqs_io.bus_hold = "false",
//           dqs_io.ddio_mode = "output",
//           dqs_io.ddioinclk_input = "negated_inclk",
//           dqs_io.dqs_ctrl_latches_enable = "true",
//           dqs_io.dqs_delay_buffer_mode = gSTRATIXII_DLL_DELAY_BUFFER_MODE,
//           dqs_io.dqs_edge_detect_enable = "false",
//           dqs_io.dqs_input_frequency = gDLL_INPUT_FREQUENCY,
//           dqs_io.dqs_offsetctrl_enable = "false",
//           dqs_io.dqs_out_mode = gSTRATIXII_DQS_OUT_MODE,
//           dqs_io.dqs_phase_shift = 9000,
//           dqs_io.extend_oe_disable = "true",
//           dqs_io.gated_dqs = "true",
//           dqs_io.inclk_input = "dqs_bus",
//           dqs_io.input_async_reset = "preset",
//           dqs_io.input_power_up = "high",
//           dqs_io.input_register_mode = "register",
//           dqs_io.input_sync_reset = "clear",
//           dqs_io.lpm_type = "stratixii_io",
//           dqs_io.oe_async_reset = "none",
//           dqs_io.oe_power_up = "low",
//           dqs_io.oe_register_mode = "register",
//           dqs_io.oe_sync_reset = "none",
//           dqs_io.open_drain_output = "false",
//           dqs_io.operation_mode = "bidir",
//           dqs_io.output_async_reset = "none",
//           dqs_io.output_power_up = "low",
//           dqs_io.output_register_mode = "register",
//           dqs_io.output_sync_reset = "none",
//           dqs_io.sim_dqs_delay_increment = 36,
//           dqs_io.sim_dqs_intrinsic_delay = 900,
//           dqs_io.sim_dqs_offset_increment = 0,
//           dqs_io.tie_off_oe_clock_enable = "false",
//           dqs_io.tie_off_output_clock_enable = "false";
//
//synthesis read_comments_as_HDL off

endmodule