ddr2_v340_ecc.fit.summary

来自「基于SIIGX的PCIe的Kit」· SUMMARY 代码 · 共 18 行

Fitter Status : Successful - Fri Jun 23 16:11:30 2006
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : ddr2_v340_ecc
Top-level Entity Name : ddr2_mfg_test
Family : Stratix II GX
Device : EP2SGX90FF1508C3
Timing Models : Preliminary
Total ALUTs : 4,449 / 72,768 ( 6 % )
Total registers : 2937
Total pins : 145 / 739 ( 20 % )
Total virtual pins : 0
Total memory bits : 1,096,992 / 4,520,448 ( 24 % )
DSP block 9-bit elements : 8 / 384 ( 2 % )
Total GXB Receiver Channels : 0 / 16 ( 0 % )
Total GXB Transmitter Channels : 0 / 16 ( 0 % )
Total PLLs : 1 / 8 ( 13 % )
Total DLLs : 1 / 2 ( 50 % )