ddr2_v340_ecc.tan.summary

基于SIIGX的PCIe的Kit

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 2.133 ns
From           : altera_internal_jtag~SHIFTUSER
To             : ddr2_cpu:inst1|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[15]
From Clock     : --
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 4.982 ns
From           : ddr2_v340_ecc:inst|heartbeat_reg[25]
To             : heartbeat
From Clock     : clock_source
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : 0.455 ns
Required Time  : 1.600 ns
Actual Time    : 1.145 ns
From           : ddr2_v340_ecc:inst|ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:3:g_ddr_io|dq_captured_rising[1]
To             : ddr2_v340_ecc:inst|ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:3:g_ddr_io|resynched_data[1]
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 1.941 ns
From           : altera_internal_jtag
To             : sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[9]
From Clock     : --
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Setup: 'ddr2_v340_ecc:inst|ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0'
Slack          : -1.185 ns
Required Time  : 333.33 MHz ( period = 3.000 ns )
Actual Time    : 238.95 MHz ( period = 4.185 ns )
From           : ddr2_v340_ecc:inst|ddr2_topecc_example_driver:driver|state.1010~DUPLICATE
To             : ddr2_v340_ecc:inst|ddr2_topecc_example_driver:driver|Add4~161_OTERM3170
From Clock     : ddr2_v340_ecc:inst|ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0
To Clock       : ddr2_v340_ecc:inst|ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0
Failed Paths   : 1663

Type           : Clock Setup: 'clock_source'
Slack          : -0.914 ns
Required Time  : 100.00 MHz ( period = 10.000 ns )
Actual Time    : N/A
From           : ddr2_v340_ecc:inst|ddr2_topecc_example_driver:driver|test_complete
To             : ddr2_cpu:inst1|test_status:the_test_status|readdata[0]
From Clock     : ddr2_v340_ecc:inst|ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0
To Clock       : clock_source
Failed Paths   : 3

Type           : Clock Setup: 'ddr2_v340_ecc:inst|ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk1'
Slack          : 0.386 ns
Required Time  : 333.33 MHz ( period = 3.000 ns )
Actual Time    : N/A
From           : ddr2_v340_ecc:inst|ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|wdata_r[11]
To             : ddr2_v340_ecc:inst|ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|\g_dq_io:3:dq_io~ddio_data_in_reg
From Clock     : ddr2_v340_ecc:inst|ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0
To Clock       : ddr2_v340_ecc:inst|ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk1
Failed Paths   : 0

Type           : Clock Setup: 'altera_internal_jtag~TCKUTAP'
Slack          : 2.684 ns
Required Time  : 100.00 MHz ( period = 10.000 ns )
Actual Time    : 215.89 MHz ( period = 4.632 ns )
From           : sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0]
To             : sld_hub:sld_hub_inst|hub_tdo
From Clock     : altera_internal_jtag~TCKUTAP
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Hold: 'ddr2_v340_ecc:inst|ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0'
Slack          : 0.018 ns
Required Time  : 333.33 MHz ( period = 3.000 ns )
Actual Time    : N/A
From           : ddr2_v340_ecc:inst|ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|init_200us_done
To             : ddr2_v340_ecc:inst|ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|cke2[0]
From Clock     : ddr2_v340_ecc:inst|ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0
To Clock       : ddr2_v340_ecc:inst|ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Clock Hold: 'clock_source'
Slack          : 0.018 ns
Required Time  : 100.00 MHz ( period = 10.000 ns )
Actual Time    : N/A
From           : ddr2_cpu:inst1|cpu_0:the_cpu_0|F_pc[7]
To             : ddr2_cpu:inst1|cpu_0:the_cpu_0|D_pc[7]
From Clock     : clock_source
To Clock       : clock_source
Failed Paths   : 0

Type           : Clock Hold: 'altera_internal_jtag~TCKUTAP'
Slack          : 0.018 ns
Required Time  : 100.00 MHz ( period = 10.000 ns )
Actual Time    : N/A
From           : sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[9]
To             : sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[8]
From Clock     : altera_internal_jtag~TCKUTAP
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Hold: 'ddr2_v340_ecc:inst|ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk1'
Slack          : 1.102 ns
Required Time  : 333.33 MHz ( period = 3.000 ns )
Actual Time    : N/A
From           : ddr2_v340_ecc:inst|ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:4:g_ddr_io|doing_rd_delayed
To             : ddr2_v340_ecc:inst|ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:3:g_ddr_io|dq_enable_reset[0]
From Clock     : ddr2_v340_ecc:inst|ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk0
To Clock       : ddr2_v340_ecc:inst|ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk1
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 1666

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