ddr2_topecc_pre_compile_ddr_timing_summary.txt

来自「基于SIIGX的PCIe的Kit」· 文本 代码 · 共 5 行

NOTE:     Speed Grade c3 used for analysis
NOTE:     For a 'Custom' memory device, please ensure that your chosen CL is compatible with your clock speed selection
WARNING:  Fed-back clock mode is recommended for frequencies greater than 200MHz.
CRITWARNING:  Warning: One or more timing requirements not met. Click 'Show Timing Estimates' for more details