ddr2_topecc_auk_ddr_dll.v

基于SIIGX的PCIe的Kit

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//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
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//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
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// synthesis translate_off
`timescale 1ps / 1ps
// synthesis translate_on

// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module ddr2_topecc_auk_ddr_dll (
                                 // inputs:
                                  clk,
                                  reset_n,
                                  stratix_dll_control,

                                 // outputs:
                                  delayctrlout,
                                  dqsupdate
                               )
;

  output  [  5: 0] delayctrlout;
  output           dqsupdate;
  input            clk;
  input            reset_n;
  input            stratix_dll_control;

  wire    [  5: 0] delayctrlout;
  wire             dqsupdate;
  //------------------------------------------------------------
  //Instantiate Stratix II DLL
  //------------------------------------------------------------

  stratixii_dll dll
    (
      .addnsub (),
      .aload (),
      .clk (clk),
      .delayctrlout (delayctrlout),
      .devclrn (),
      .devpor (),
      .dqsupdate (dqsupdate),
      .offset (),
      .offsetctrlout (),
      .upndnin (),
      .upndninclkena (),
      .upndnout ()
    );

  defparam dll.delay_buffer_mode = "high",
           dll.delay_chain_length = 12,
           dll.delayctrlout_mode = "normal",
           dll.input_frequency = "3000ps",
           dll.jitter_reduction = "false",
           dll.lpm_type = "stratixii_dll",
           dll.offsetctrlout_mode = "static",
           dll.sim_loop_delay_increment = 144,
           dll.sim_loop_intrinsic_delay = 3600,
           dll.sim_valid_lock = 1,
           dll.sim_valid_lockcount = 27,
           dll.static_delay_ctrl = 0,
           dll.static_offset = "0",
           dll.use_upndnin = "false",
           dll.use_upndninclkena = "false";


endmodule