ddr2_topecc_post_summary.txt

基于SIIGX的PCIe的Kit

NOTE: Found a clock output pin: clk_to_sdram_n[0]
NOTE: Found a clock output pin: clk_to_sdram_n[1]
NOTE: Found a clock output pin: clk_to_sdram_n[2]
NOTE: Found a clock output pin: clk_to_sdram_p[0]
NOTE: Found a clock output pin: clk_to_sdram_p[1]
NOTE: Found a clock output pin: clk_to_sdram_p[2]
Running DDR system timing analysis equations.. pwd:C:/cvs_sandbox/boards/stratix2_gx/stratix2_gx_pciex/pld/ddr2/ddr2_v340_ecc
NOTE:     Speed Grade c3 used for analysis
NOTE:     For a 'Custom' memory device, please ensure that your chosen CL is compatible with your clock speed selection
WARNING:  Fed-back clock mode is recommended for frequencies greater than 200MHz.
  
 DDR read data capture: DDR Data to DQS strobe edges at capture registers. 
             Setup slack is   264 ps    associated with pin 'ddr2_dq[0]'  ( variation port 'dq(0)', 'dq_captured_falling')              
             Hold slack is     92 ps    associated with pin 'ddr2_dq[0]'  ( variation port 'dq(0)', 'dq_captured_rising')              
  
 Read data resynchronisation: Captured data to resync clock at resync registers ('resynched_data').  
WARNING:         Setup slack is  -577 ps    associated with pin 'ddr2_dq[40]'  ( variation port 'dq(40)', 'dq_captured_falling') ( Total of 144 paths with negative slack)    
WARNING:         Hold slack is   -282 ps    associated with pin 'ddr2_dq[3]'  ( variation port 'dq(3)', 'dq_captured_rising') ( Total of 144 paths with negative slack)
  
 Read Postamble Enable: Enable-release to DQS strobe postamble period at negative-edge capture registers.  
             Setup slack is   387 ps    associated with pin 'ddr2_dq[0]'  ( variation port 'dq(0)', 'dq_captured_rising')                  
             Hold slack is guaranteed by design to always be positive for Stratix II
  
 Read Postamble Control: Preset-release ('dq_enable_reset') to DQS strobe negative edges at postamble register ('dq_enable').       
             Setup slack is   948 ps    associated with pin 'ddr2_dq[24]'  ( variation port 'dq(24)', 'dq_captured_rising')                  
             Hold slack is    204 ps    associated with pin 'ddr2_dq[32]'  ( variation port 'dq(32)', 'dq_captured_rising')