ddr2_v340_ecc.qsf

基于SIIGX的PCIe的Kit

set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS II" -to ddr2_dq[39]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS II" -to ddr2_dq[40]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS II" -to ddr2_dq[41]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS II" -to ddr2_dq[42]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS II" -to ddr2_dq[43]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS II" -to ddr2_dq[44]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS II" -to ddr2_dq[45]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS II" -to ddr2_dq[46]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS II" -to ddr2_dq[47]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS II" -to ddr2_dq[48]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS II" -to ddr2_dq[49]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS II" -to ddr2_dq[50]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS II" -to ddr2_dq[51]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS II" -to ddr2_dq[52]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS II" -to ddr2_dq[53]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS II" -to ddr2_dq[54]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS II" -to ddr2_dq[55]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS II" -to ddr2_dq[56]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS II" -to ddr2_dq[57]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS II" -to ddr2_dq[58]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS II" -to ddr2_dq[59]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS II" -to ddr2_dq[60]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS II" -to ddr2_dq[61]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS II" -to ddr2_dq[62]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS II" -to ddr2_dq[63]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS II" -to ddr2_dq[64]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS II" -to ddr2_dq[65]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS II" -to ddr2_dq[66]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS II" -to ddr2_dq[67]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS II" -to ddr2_dq[68]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS II" -to ddr2_dq[69]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS II" -to ddr2_dq[70]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS II" -to ddr2_dq[71]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS II" -to ddr2_dqs[0]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS II" -to ddr2_dqs[1]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS II" -to ddr2_dqs[2]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS II" -to ddr2_dqs[3]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS II" -to ddr2_dqs[4]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS II" -to ddr2_dqs[5]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS II" -to ddr2_dqs[6]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS II" -to ddr2_dqs[7]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS II" -to ddr2_dqs[8]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS II" -to clk_to_sdram_p[0]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS II" -to clk_to_sdram_p[1]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS II" -to clk_to_sdram_p[2]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS II" -to clk_to_sdram_n[0]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS II" -to clk_to_sdram_n[1]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS II" -to clk_to_sdram_n[2]
set_instance_assignment -name IO_STANDARD LVDS -to clock_source
set_location_assignment PIN_AW19 -to clk_to_sdram_p[0]
set_location_assignment PIN_AU20 -to clk_to_sdram_p[1]
set_location_assignment PIN_AP20 -to clk_to_sdram_p[2]
set_location_assignment PIN_AV19 -to clk_to_sdram_n[0]
set_location_assignment PIN_AT20 -to clk_to_sdram_n[1]
set_location_assignment PIN_AN20 -to clk_to_sdram_n[2]
set_global_assignment -name ASSIGNMENT_GROUP_MEMBER clk_to_sdram_p[0] -section_id ddr2_topecc_clk_out_pair0
set_global_assignment -name ASSIGNMENT_GROUP_MEMBER clk_to_sdram_p[1] -section_id ddr2_topecc_clk_out_pair1
set_global_assignment -name ASSIGNMENT_GROUP_MEMBER clk_to_sdram_p[2] -section_id ddr2_topecc_clk_out_pair2
set_global_assignment -name ASSIGNMENT_GROUP_MEMBER clk_to_sdram_n[0] -section_id ddr2_topecc_clk_out_pair0
set_global_assignment -name ASSIGNMENT_GROUP_MEMBER clk_to_sdram_n[1] -section_id ddr2_topecc_clk_out_pair1
set_global_assignment -name ASSIGNMENT_GROUP_MEMBER clk_to_sdram_n[2] -section_id ddr2_topecc_clk_out_pair2
set_location_assignment PIN_AU9 -to ddr2_dq[0]
set_location_assignment LAB_X80_Y1 -to "ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io|resynched_data[0]"
set_location_assignment LAB_X80_Y1 -to "ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io|resynched_data[8]"
set_location_assignment LAB_X80_Y2 -to "ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io|dq_enable_reset[0]"
set_location_assignment PIN_AN10 -to ddr2_dq[1]
set_location_assignment LAB_X80_Y1 -to "ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io|resynched_data[1]"
set_location_assignment LAB_X80_Y1 -to "ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io|resynched_data[9]"
set_location_assignment PIN_AP10 -to ddr2_dq[2]
set_location_assignment LAB_X83_Y1 -to "ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io|resynched_data[2]"
set_location_assignment LAB_X83_Y1 -to "ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io|resynched_data[10]"
set_location_assignment PIN_AW9 -to ddr2_dq[3]
set_location_assignment LAB_X83_Y1 -to "ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io|resynched_data[3]"
set_location_assignment LAB_X83_Y1 -to "ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io|resynched_data[11]"
set_location_assignment PIN_AV10 -to ddr2_dq[4]
set_location_assignment LAB_X83_Y1 -to "ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io|resynched_data[4]"
set_location_assignment LAB_X83_Y1 -to "ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io|resynched_data[12]"
set_location_assignment PIN_AU10 -to ddr2_dq[5]
set_location_assignment LAB_X84_Y1 -to "ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io|resynched_data[5]"
set_location_assignment LAB_X84_Y1 -to "ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io|resynched_data[13]"
set_location_assignment PIN_AN11 -to ddr2_dq[6]
set_location_assignment LAB_X86_Y1 -to "ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io|resynched_data[6]"
set_location_assignment LAB_X86_Y1 -to "ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io|resynched_data[14]"
set_location_assignment PIN_AW10 -to ddr2_dq[7]
set_location_assignment LAB_X86_Y1 -to "ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io|resynched_data[7]"
set_location_assignment LAB_X86_Y1 -to "ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:0:g_ddr_io|resynched_data[15]"
set_location_assignment PIN_AT9 -to ddr2_dqs[0]
set_location_assignment PIN_AT11 -to ddr2_dm[0]
set_location_assignment PIN_AT12 -to ddr2_dq[8]
set_location_assignment LAB_X75_Y1 -to "ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:1:g_ddr_io|resynched_data[0]"
set_location_assignment LAB_X75_Y1 -to "ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:1:g_ddr_io|resynched_data[8]"
set_location_assignment LAB_X75_Y2 -to "ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:1:g_ddr_io|dq_enable_reset[0]"
set_location_assignment PIN_AW11 -to ddr2_dq[9]
set_location_assignment LAB_X75_Y1 -to "ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:1:g_ddr_io|resynched_data[1]"
set_location_assignment LAB_X75_Y1 -to "ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:1:g_ddr_io|resynched_data[9]"
set_location_assignment PIN_AR12 -to ddr2_dq[10]
set_location_assignment LAB_X76_Y1 -to "ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:1:g_ddr_io|resynched_data[2]"
set_location_assignment LAB_X76_Y1 -to "ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:1:g_ddr_io|resynched_data[10]"
set_location_assignment PIN_AW12 -to ddr2_dq[11]
set_location_assignment LAB_X76_Y1 -to "ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:1:g_ddr_io|resynched_data[3]"
set_location_assignment LAB_X76_Y1 -to "ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:1:g_ddr_io|resynched_data[11]"
set_location_assignment PIN_AN13 -to ddr2_dq[12]
set_location_assignment LAB_X76_Y1 -to "ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:1:g_ddr_io|resynched_data[4]"
set_location_assignment LAB_X76_Y1 -to "ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\\g_datapath:1:g_ddr_io|resynched_data[12]"