ddr2_v340_ecc.map.rpt

基于SIIGX的PCIe的Kit

Analysis & Synthesis report for ddr2_v340_ecc
Fri Jun 23 15:23:15 2006
Version 6.0 Build 178 04/27/2006 SJ Full Version


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; Table of Contents ;
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  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Analysis & Synthesis RAM Summary
  8. Analysis & Synthesis DSP Block Usage Summary
  9. State Machine - |ddr2_mfg_test|ddr2_v340_ecc:inst|ddr2_topecc_example_driver:driver|state
 10. State Machine - |ddr2_mfg_test|ddr2_v340_ecc:inst|ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|state
 11. State Machine - |ddr2_mfg_test|ddr2_v340_ecc:inst|ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|auk_ddr2_init:\g_ddr2_init:init_block|ddr2_init_state
 12. Registers Protected by Synthesis
 13. General Register Statistics
 14. Inverted Register Statistics
 15. Multiplexer Restructuring Statistics (No Restructuring Performed)
 16. Source assignments for ddr2_v340_ecc:inst|ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control
 17. Source assignments for ddr2_v340_ecc:inst|ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|scfifo:\g_local_buffered_if:reg_wdata_fifo|scfifo_e691:auto_generated|a_dpfifo_7u11:dpfifo|altsyncram_a6e1:FIFOram
 18. Source assignments for ddr2_v340_ecc:inst|ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|auk_ddr2_init:\g_ddr2_init:init_block
 19. Source assignments for ddr2_v340_ecc:inst|ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_clk_gen:ddr_clk_gen|altddio_out:ddr_clk_out_p
 20. Source assignments for ddr2_v340_ecc:inst|ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_clk_gen:ddr_clk_gen|altddio_out:ddr_clk_out_n
 21. Source assignments for ddr2_v340_ecc:inst|ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io
 22. Source assignments for ddr2_v340_ecc:inst|ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_out:dm_pin
 23. Source assignments for ddr2_v340_ecc:inst|ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io
 24. Source assignments for ddr2_v340_ecc:inst|ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_out:dm_pin
 25. Source assignments for ddr2_v340_ecc:inst|ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:2:g_ddr_io
 26. Source assignments for ddr2_v340_ecc:inst|ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:2:g_ddr_io|altddio_out:dm_pin
 27. Source assignments for ddr2_v340_ecc:inst|ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:3:g_ddr_io
 28. Source assignments for ddr2_v340_ecc:inst|ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:3:g_ddr_io|altddio_out:dm_pin
 29. Source assignments for ddr2_v340_ecc:inst|ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:4:g_ddr_io
 30. Source assignments for ddr2_v340_ecc:inst|ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:4:g_ddr_io|altddio_out:dm_pin
 31. Source assignments for ddr2_v340_ecc:inst|ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:5:g_ddr_io
 32. Source assignments for ddr2_v340_ecc:inst|ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:5:g_ddr_io|altddio_out:dm_pin
 33. Source assignments for ddr2_v340_ecc:inst|ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:6:g_ddr_io
 34. Source assignments for ddr2_v340_ecc:inst|ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:6:g_ddr_io|altddio_out:dm_pin
 35. Source assignments for ddr2_v340_ecc:inst|ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:7:g_ddr_io
 36. Source assignments for ddr2_v340_ecc:inst|ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:7:g_ddr_io|altddio_out:dm_pin
 37. Source assignments for ddr2_v340_ecc:inst|ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:8:g_ddr_io
 38. Source assignments for ddr2_v340_ecc:inst|ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:8:g_ddr_io|altddio_out:dm_pin
 39. Source assignments for ddr2_cpu:inst1|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_d7c1:auto_generated
 40. Source assignments for ddr2_cpu:inst1|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram|altsyncram_4ue1:auto_generated
 41. Source assignments for ddr2_cpu:inst1|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram|altsyncram_5ke1:auto_generated
 42. Source assignments for ddr2_cpu:inst1|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram|altsyncram_6ke1:auto_generated
 43. Source assignments for ddr2_cpu:inst1|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_de72:auto_generated
 44. Source assignments for ddr2_cpu:inst1|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_fe02:auto_generated
 45. Source assignments for ddr2_cpu:inst1|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_6031:auto_generated|a_dpfifo_9631:dpfifo|dpram_6q21:FIFOram|altsyncram_a6m1:altsyncram2
 46. Source assignments for ddr2_cpu:inst1|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_6031:auto_generated|a_dpfifo_9631:dpfifo|dpram_6q21:FIFOram|altsyncram_a6m1:altsyncram2
 47. Source assignments for ddr2_cpu:inst1|onchip_memory_0:the_onchip_memory_0|altsyncram:the_altsyncram|altsyncram_2r71:auto_generated
 48. Source assignments for ddr2_cpu:inst1|ddr2_cpu_reset_clk_domain_synch_module:ddr2_cpu_reset_clk_domain_synch
 49. Source assignments for sld_hub:sld_hub_inst
 50. Source assignments for sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine
 51. Source assignments for sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG
 52. Parameter Settings for User Entity Instance: ddr2_v340_ecc:inst|ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst
 53. Parameter Settings for User Entity Instance: ddr2_v340_ecc:inst|ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control
 54. Parameter Settings for User Entity Instance: ddr2_v340_ecc:inst|ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|scfifo:\g_local_buffered_if:reg_wdata_fifo
 55. Parameter Settings for User Entity Instance: ddr2_v340_ecc:inst|ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|auk_ddr_input_buf:in_buf
 56. Parameter Settings for User Entity Instance: ddr2_v340_ecc:inst|ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|auk_ddr_input_buf:in_buf|custom_fifo:my_fifo
 57. Parameter Settings for User Entity Instance: ddr2_v340_ecc:inst|ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|auk_ddr_bank_details:bank_man
 58. Parameter Settings for User Entity Instance: ddr2_v340_ecc:inst|ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|auk_ddr2_init:\g_ddr2_init:init_block
 59. Parameter Settings for User Entity Instance: ddr2_v340_ecc:inst|ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|auk_ddr_timers:\g_timers:0:bank_timer
 60. Parameter Settings for User Entity Instance: ddr2_v340_ecc:inst|ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|auk_ddr_timers:\g_timers:1:bank_timer
 61. Parameter Settings for User Entity Instance: ddr2_v340_ecc:inst|ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|auk_ddr_timers:\g_timers:2:bank_timer
 62. Parameter Settings for User Entity Instance: ddr2_v340_ecc:inst|ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|auk_ddr_controller:ddr_control|auk_ddr_timers:\g_timers:3:bank_timer
 63. Parameter Settings for User Entity Instance: ddr2_v340_ecc:inst|ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io
 64. Parameter Settings for User Entity Instance: ddr2_v340_ecc:inst|ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_clk_gen:ddr_clk_gen|altddio_out:ddr_clk_out_p
 65. Parameter Settings for User Entity Instance: ddr2_v340_ecc:inst|ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_clk_gen:ddr_clk_gen|altddio_out:ddr_clk_out_n
 66. Parameter Settings for User Entity Instance: ddr2_v340_ecc:inst|ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io
 67. Parameter Settings for User Entity Instance: ddr2_v340_ecc:inst|ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_out:dm_pin
 68. Parameter Settings for User Entity Instance: ddr2_v340_ecc:inst|ddr2_topecc:ddr2_topecc_ddr_sdram|ddr2_topecc_auk_ddr_sdram:ddr2_topecc_auk_ddr_sdram_inst|ddr2_topecc_auk_ddr_datapath:ddr_io|ddr2_topecc_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io