ddr2_cpu_log.txt

基于SIIGX的PCIe的Kit

Altera SOPC Builder Version 6.00 Build 178
Copyright (c) 1999-2006 Altera Corporation.  All rights reserved.


# 2006.06.23 15:12:29 (*) mk_custom_sdk starting
# 2006.06.23 15:12:29 (*) Reading project C:/cvs_sandbox/boards/stratix2_gx/stratix2_gx_pciex/pld/ddr2/ddr2_v340_ecc/ddr2_v340_ecc_restored/ddr2_cpu.ptf.

# 2006.06.23 15:12:29 (*) Finding all CPUs
# 2006.06.23 15:12:29 (*) Finding all available components
# 2006.06.23 15:12:29 (*) Reading C:/cvs_sandbox/boards/stratix2_gx/stratix2_gx_pciex/pld/ddr2/ddr2_v340_ecc/ddr2_v340_ecc_restored/.sopc_builder/install.ptf

# 2006.06.23 15:12:29 (*) Found 62 components

# 2006.06.23 15:12:30 (*) Finding all peripherals

# 2006.06.23 15:12:30 (*) Finding software components

# 2006.06.23 15:12:31 (*) (Legacy SDK Generation Skipped)
# 2006.06.23 15:12:31 (*) (All TCL Script Generation Skipped)
# 2006.06.23 15:12:31 (*) (No Libraries Built)
# 2006.06.23 15:12:31 (*) (Contents Generation Skipped)
# 2006.06.23 15:12:31 (*) mk_custom_sdk finishing

# 2006.06.23 15:12:31 (*) Starting generation for system: ddr2_cpu.

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# 2006.06.23 15:12:33 (*) Running Generator Program for cpu_0

# 2006.06.23 15:12:36 (*)   Checking for plaintext license.
# 2006.06.23 15:12:36 (*)   Plaintext license not found.
# 2006.06.23 15:12:36 (*)   Checking for encrypted license (non-evaluation).
# 2006.06.23 15:12:37 (*)   Encrypted license found.  SOF will not be time-limited.
# 2006.06.23 15:13:07 (*)   Creating encrypted HDL

# 2006.06.23 15:13:13 (*) Running Generator Program for jtag_uart_0

# 2006.06.23 15:13:15 (*) Running Generator Program for onchip_memory_0

# 2006.06.23 15:13:17 (*) Running Generator Program for timer_0

# 2006.06.23 15:13:18 (*) Running Generator Program for timer_1

# 2006.06.23 15:13:20 (*) Running Generator Program for test_status

# 2006.06.23 15:13:21 (*) Running Generator Program for test_start


# 2006.06.23 15:13:22 (*) Making arbitration and system (top) modules.

# 2006.06.23 15:13:31 (*) Generating Quartus symbol for top level: ddr2_cpu

# 2006.06.23 15:13:31 (*) Generating Symbol C:/cvs_sandbox/boards/stratix2_gx/stratix2_gx_pciex/pld/ddr2/ddr2_v340_ecc/ddr2_v340_ecc_restored/ddr2_cpu.bsf

# 2006.06.23 15:13:31 (*) Creating command-line system-generation script: C:/cvs_sandbox/boards/stratix2_gx/stratix2_gx_pciex/pld/ddr2/ddr2_v340_ecc/ddr2_v340_ecc_restored/ddr2_cpu_generation_script

# 2006.06.23 15:13:31 (*) Running setup for HDL simulator: modelsim


# 2006.06.23 15:13:31 (*) Setting up Quartus with ddr2_cpu_setup_quartus.tcl
c:/altera/quartus60/bin/quartus_sh -t ddr2_cpu_setup_quartus.tcl


Info: *******************************************************************
Info: Running Quartus II Shell
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Copyright (C) 1991-2006 Altera Corporation. All rights reserved.
    Info: Your use of Altera Corporation's design tools, logic functions 
    Info: and other software and tools, and its AMPP partner logic 
    Info: functions, and any output files any of the foregoing 
    Info: (including device programming or simulation files), and any 
    Info: associated documentation or information are expressly subject 
    Info: to the terms and conditions of the Altera Program License 
    Info: Subscription Agreement, Altera MegaCore Function License 
    Info: Agreement, or other applicable license agreement, including, 
    Info: without limitation, that your use is for the sole purpose of 
    Info: programming logic devices manufactured by Altera and sold by 
    Info: Altera or its authorized distributors.  Please refer to th
e 
    Info: applicable agreement for further details.
    Info: Processing started: Fri Jun 23 15:13:31 2006
Info: Command: quartus_sh -t ddr2_cpu_setup_quartus.tcl
Info: Evaluation of Tcl script ddr2_cpu_setup_quartus.tcl was successful
Info: Quartus II Shell was successful. 0 errors, 0 warnings
    Info: Processing ended: Fri Jun 23 15:13:31 2006
    Info: Elapsed time: 00:00:00

# 2006.06.23 15:13:32 (*) Completed generation for system: ddr2_cpu.
# 2006.06.23 15:13:32 (*) THE FOLLOWING SYSTEM ITEMS HAVE BEEN GENERATED:
  SOPC Builder database : C:/cvs_sandbox/boards/stratix2_gx/stratix2_gx_pciex/pld/ddr2/ddr2_v340_ecc/ddr2_v340_ecc_restored/ddr2_cpu.ptf 
  System HDL Model : C:/cvs_sandbox/boards/stratix2_gx/stratix2_gx_pciex/pld/ddr2/ddr2_v340_ecc/ddr2_v340_ecc_restored/ddr2_cpu.vhd 
  System Generation Script : C:/cvs_sandbox/boards/stratix2_gx/stratix2_gx_pciex/pld/ddr2/ddr2_v340_ecc/ddr2_v340_ecc_restored/ddr2_cpu_generation_script 


# 2006.06.23 15:13:32 (*) SUCCESS: SYSTEM GENERATION COMPLETED.


Press 'Exit' to exit.