sso_block.v

基于SIIGX的PCIe的Kit

// Copyright (C) 1991-2004 Altera Corporation
// Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
// support information,  device programming or simulation file,  and any other
// associated  documentation or information  provided by  Altera  or a partner
// under  Altera's   Megafunction   Partnership   Program  may  be  used  only
// to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
// other  use  of such  megafunction  design,  netlist,  support  information,
// device programming or simulation file,  or any other  related documentation
// or information  is prohibited  for  any  other purpose,  including, but not
// limited to  modification,  reverse engineering,  de-compiling, or use  with
// any other  silicon devices,  unless such use is  explicitly  licensed under
// a separate agreement with  Altera  or a megafunction partner.  Title to the
// intellectual property,  including patents,  copyrights,  trademarks,  trade
// secrets,  or maskworks,  embodied in any such megafunction design, netlist,
// support  information,  device programming or simulation file,  or any other
// related documentation or information provided by  Altera  or a megafunction
// partner, remains with Altera, the megafunction partner, or their respective
// licensors. No other licenses, including any licenses needed under any third
// party's intellectual property, are provided herein.

module sso_block(
	enable,
	clock,
	output0,
	output1,
	output2,
	output3,
	output4,
	output5,
	output6,
	output7,
	output8,
	output9
);

input	enable;
input	clock;
output	output0;
reg	output0;
output	output1;
reg	output1;
output	output2;
reg	output2;
output	output3;
reg	output3;
output	output4;
reg	output4;
output	output5;
reg	output5;
output	output6;
reg	output6;
output	output7;
reg	output7;
output	output8;
reg	output8;
output	output9;
reg	output9;






always@(posedge clock)
begin
	output5 = output5 ^ enable;
end

always@(posedge clock)
begin
	output7 = output7 ^ enable;
end

always@(posedge clock)
begin
	output6 = output6 ^ enable;
end

always@(posedge clock)
begin
	output8 = output8 ^ enable;
end

always@(posedge clock)
begin
	output0 = output0 ^ enable;
end

always@(posedge clock)
begin
	output9 = output9 ^ enable;
end

always@(posedge clock)
begin
	output1 = output1 ^ enable;
end

always@(posedge clock)
begin
	output3 = output3 ^ enable;
end

always@(posedge clock)
begin
	output2 = output2 ^ enable;
end

always@(posedge clock)
begin
	output4 = output4 ^ enable;
end


endmodule