thermal_top.map.rpt

基于SIIGX的PCIe的Kit

Analysis & Synthesis report for thermal_top
Mon Apr 17 14:40:17 2006
Version 6.0 Internal Build 165 03/22/2006 SJ Full Version


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; Table of Contents ;
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  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. State Machine - |thermal_top|thermal:b2v_inst3|state
  8. General Register Statistics
  9. Inverted Register Statistics
 10. Multiplexer Restructuring Statistics (Restructuring Performed)
 11. Source assignments for divide_by_10:b2v_inst04|lpm_divide:lpm_divide_component|lpm_divide_jqt:auto_generated|sign_div_unsign_s5i:divider|alt_u_div_ksf:divider
 12. Parameter Settings for User Entity Instance: bus_mux2:b2v_inst|lpm_mux:lpm_mux_component
 13. Parameter Settings for User Entity Instance: divide_by_10:b2v_inst04|lpm_divide:lpm_divide_component
 14. Parameter Settings for User Entity Instance: lpm_counter_10bit:b2v_inst09|lpm_counter:lpm_counter_component
 15. Parameter Settings for User Entity Instance: thermal:b2v_inst3
 16. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                       ;
+--------------------------------+---------------------------------------------------+
; Analysis & Synthesis Status    ; Successful - Mon Apr 17 14:40:17 2006             ;
; Quartus II Version             ; 6.0 Internal Build 165 03/22/2006 SJ Full Version ;
; Revision Name                  ; thermal_top                                       ;
; Top-level Entity Name          ; thermal_top                                       ;
; Family                         ; Stratix II GX                                     ;
; Total ALUTs                    ; 256                                               ;
; Total registers                ; 123                                               ;
; Total pins                     ; 14                                                ;
; Total virtual pins             ; 0                                                 ;
; Total memory bits              ; 0                                                 ;
; DSP block 9-bit elements       ; 0                                                 ;
; Total GXB Receiver Channels    ; 0                                                 ;
; Total GXB Transmitter Channels ; 0                                                 ;
; Total PLLs                     ; 0                                                 ;
; Total DLLs                     ; 0                                                 ;
+--------------------------------+---------------------------------------------------+


+------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                        ;
+------------------------------------------------------------+--------------------+--------------------+
; Option                                                     ; Setting            ; Default Value      ;
+------------------------------------------------------------+--------------------+--------------------+
; Device                                                     ; EP2SGX90FF1508C3   ;                    ;
; Top-level entity name                                      ; thermal_top        ; thermal_top        ;
; Family name                                                ; Stratix II GX      ; Stratix            ;
; Use smart compilation                                      ; Off                ; Off                ;
; Restructure Multiplexers                                   ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                        ; Off                ; Off                ;
; Preserve fewer node names                                  ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                  ; Off                ; Off                ;
; Verilog Version                                            ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                               ; VHDL93             ; VHDL93             ;
; State Machine Processing                                   ; Auto               ; Auto               ;
; Extract Verilog State Machines                             ; On                 ; On                 ;
; Extract VHDL State Machines                                ; On                 ; On                 ;
; Add Pass-Through Logic to Inferred RAMs                    ; On                 ; On                 ;
; DSP Block Balancing                                        ; Auto               ; Auto               ;
; Maximum DSP Block Usage                                    ; Unlimited          ; Unlimited          ;
; NOT Gate Push-Back                                         ; On                 ; On                 ;
; Power-Up Don't Care                                        ; On                 ; On                 ;
; Remove Redundant Logic Cells                               ; Off                ; Off                ;
; Remove Duplicate Registers                                 ; On                 ; On                 ;