alt_u_div_tag.tdf

基于SIIGX的PCIe的Kit

--alt_u_div DEVICE_FAMILY="Stratix II" LPM_PIPELINE=1 MAXIMIZE_SPEED=5 SKIP_BITS=0 WIDTH_D=8 WIDTH_N=8 WIDTH_Q=8 WIDTH_R=8 clock den_out denominator numerator quotient remainder
--VERSION_BEGIN 6.0 cbx_cycloneii 2006:02:07:15:19:20:SJ cbx_lpm_abs 2006:01:02:19:20:00:SJ cbx_lpm_add_sub 2006:01:09:11:17:20:SJ cbx_lpm_divide 2006:01:18:17:01:10:SJ cbx_mgl 2006:03:24:09:13:16:SJ cbx_stratix 2006:02:07:15:17:04:SJ cbx_stratixii 2006:03:03:09:35:36:SJ cbx_util_mgl 2006:01:09:10:46:36:SJ  VERSION_END


--  Copyright (C) 1991-2006 Altera Corporation
--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
--  Altera or its authorized distributors.  Please refer to the 
--  applicable agreement for further details.



--synthesis_resources = lut 44 reg 32 
OPTIONS ALTERA_INTERNAL_OPTION = "{-to DFFQuotient[0]} POWER_UP_LEVEL=HIGH;{-to DFFQuotient[1]} POWER_UP_LEVEL=HIGH;{-to DFFQuotient[2]} POWER_UP_LEVEL=HIGH;{-to DFFQuotient[3]} POWER_UP_LEVEL=HIGH;{-to DFFQuotient[4]} POWER_UP_LEVEL=LOW;{-to DFFQuotient[5]} POWER_UP_LEVEL=LOW;{-to DFFQuotient[6]} POWER_UP_LEVEL=LOW;{-to DFFQuotient[7]} POWER_UP_LEVEL=LOW;{-to DFFDenominator} POWER_UP_LEVEL=HIGH";

SUBDESIGN alt_u_div_tag
( 
	clock	:	input;
	den_out[7..0]	:	output;
	denominator[7..0]	:	input;
	numerator[7..0]	:	input;
	quotient[7..0]	:	output;
	remainder[7..0]	:	output;
) 
VARIABLE 
	DFFDenominator[7..0] : dffe
		WITH (
			POWER_UP_HIGH = "ON"
		);
	DFFNumerator[7..0] : dffe;
	DFFQuotient[7..0] : dffe;
	DFFStage[7..0] : dffe;
	add_sub_0_result_int[1..0]	:	WIRE;
	add_sub_0_cout	:	WIRE;
	add_sub_0_dataa[0..0]	:	WIRE;
	add_sub_0_datab[0..0]	:	WIRE;
	add_sub_0_result[0..0]	:	WIRE;
	add_sub_1_result_int[2..0]	:	WIRE;
	add_sub_1_cout	:	WIRE;
	add_sub_1_dataa[1..0]	:	WIRE;
	add_sub_1_datab[1..0]	:	WIRE;
	add_sub_1_result[1..0]	:	WIRE;
	add_sub_2_result_int[3..0]	:	WIRE;
	add_sub_2_cout	:	WIRE;
	add_sub_2_dataa[2..0]	:	WIRE;
	add_sub_2_datab[2..0]	:	WIRE;
	add_sub_2_result[2..0]	:	WIRE;
	add_sub_3_result_int[4..0]	:	WIRE;
	add_sub_3_cout	:	WIRE;
	add_sub_3_dataa[3..0]	:	WIRE;
	add_sub_3_datab[3..0]	:	WIRE;
	add_sub_3_result[3..0]	:	WIRE;
	add_sub_4_result_int[5..0]	:	WIRE;
	add_sub_4_cout	:	WIRE;
	add_sub_4_dataa[4..0]	:	WIRE;
	add_sub_4_datab[4..0]	:	WIRE;
	add_sub_4_result[4..0]	:	WIRE;
	add_sub_5_result_int[6..0]	:	WIRE;
	add_sub_5_cout	:	WIRE;
	add_sub_5_dataa[5..0]	:	WIRE;
	add_sub_5_datab[5..0]	:	WIRE;
	add_sub_5_result[5..0]	:	WIRE;
	add_sub_6_result_int[7..0]	:	WIRE;
	add_sub_6_cout	:	WIRE;
	add_sub_6_dataa[6..0]	:	WIRE;
	add_sub_6_datab[6..0]	:	WIRE;
	add_sub_6_result[6..0]	:	WIRE;
	add_sub_7_result_int[8..0]	:	WIRE;
	add_sub_7_cout	:	WIRE;
	add_sub_7_dataa[7..0]	:	WIRE;
	add_sub_7_datab[7..0]	:	WIRE;
	add_sub_7_result[7..0]	:	WIRE;
	aclr	: NODE;
	clk_en	: NODE;
	DenominatorIn[80..0]	: WIRE;
	DenominatorIn_tmp[80..0]	: WIRE;
	gnd_wire	: WIRE;
	nose[71..0]	: WIRE;
	NumeratorIn[71..0]	: WIRE;
	NumeratorIn_tmp[71..0]	: WIRE;
	prestg[63..0]	: WIRE;