sign_div_unsign_73h.tdf

基于SIIGX的PCIe的Kit

--sign_div_unsign DEN_REPRESENTATION="UNSIGNED" DEN_WIDTH=8 LPM_PIPELINE=1 MAXIMIZE_SPEED=5 NUM_REPRESENTATION="UNSIGNED" NUM_WIDTH=8 clock denominator numerator quotient remainder
--VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:07:00:11:16:SJ cbx_lpm_divide 2005:03:14:22:01:08:SJ cbx_mgl 2005:03:28:10:52:10:SJ cbx_stratix 2005:03:14:17:09:02:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ  VERSION_END


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--  functions, and any output files any of the foregoing 
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--  without limitation, that your use is for the sole purpose of 
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FUNCTION alt_u_div_88f (clock, denominator[7..0], numerator[7..0])
RETURNS ( den_out[7..0], quotient[7..0], remainder[7..0]);

--synthesis_resources = lut 76 
SUBDESIGN sign_div_unsign_73h
( 
	clock	:	input;
	denominator[7..0]	:	input;
	numerator[7..0]	:	input;
	quotient[7..0]	:	output;
	remainder[7..0]	:	output;
) 
VARIABLE 
	divider : alt_u_div_88f;
	adder_result_int[8..0]	:	WIRE;
	adder_cin	:	WIRE;
	adder_dataa[7..0]	:	WIRE;
	adder_datab[7..0]	:	WIRE;
	adder_result[7..0]	:	WIRE;
	adder_out[7..0]	: WIRE;
	gnd_wire	: WIRE;
	norm_num[7..0]	: WIRE;
	protect_quotient[7..0]	: WIRE;
	protect_remainder[7..0]	: WIRE;
	vcc_wire	: WIRE;

BEGIN 
	divider.clock = clock;
	divider.denominator[] = denominator[];
	divider.numerator[] = norm_num[];
	adder_result_int[] = (adder_dataa[], 0) - (adder_datab[], !adder_cin);
	adder_result[] = adder_result_int[8..1];
	adder_cin = gnd_wire;
	adder_dataa[] = divider.den_out[];
	adder_datab[] = protect_remainder[];
	adder_out[] = adder_result[];
	gnd_wire = B"0";
	norm_num[] = numerator[];
	protect_quotient[] = divider.quotient[];
	protect_remainder[] = divider.remainder[];
	quotient[] = protect_quotient[];
	remainder[] = protect_remainder[];
	vcc_wire = B"1";
END;
--VALID FILE