mux_7lb.tdf

基于SIIGX的PCIe的Kit

--lpm_mux CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Stratix II" LPM_SIZE=4 LPM_WIDTH=18 LPM_WIDTHS=2 data result sel
--VERSION_BEGIN 6.0 cbx_lpm_mux 2006:01:09:11:16:16:SJ cbx_mgl 2006:03:24:09:13:16:SJ  VERSION_END


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--synthesis_resources = lut 18 
SUBDESIGN mux_7lb
( 
	data[71..0]	:	input;
	result[17..0]	:	output;
	sel[1..0]	:	input;
) 
VARIABLE
	l1_w0_n0_mux_dataout	:	WIRE;
	l1_w0_n1_mux_dataout	:	WIRE;
	l1_w10_n0_mux_dataout	:	WIRE;
	l1_w10_n1_mux_dataout	:	WIRE;
	l1_w11_n0_mux_dataout	:	WIRE;
	l1_w11_n1_mux_dataout	:	WIRE;
	l1_w12_n0_mux_dataout	:	WIRE;
	l1_w12_n1_mux_dataout	:	WIRE;
	l1_w13_n0_mux_dataout	:	WIRE;
	l1_w13_n1_mux_dataout	:	WIRE;
	l1_w14_n0_mux_dataout	:	WIRE;
	l1_w14_n1_mux_dataout	:	WIRE;
	l1_w15_n0_mux_dataout	:	WIRE;
	l1_w15_n1_mux_dataout	:	WIRE;
	l1_w16_n0_mux_dataout	:	WIRE;
	l1_w16_n1_mux_dataout	:	WIRE;
	l1_w17_n0_mux_dataout	:	WIRE;
	l1_w17_n1_mux_dataout	:	WIRE;
	l1_w1_n0_mux_dataout	:	WIRE;
	l1_w1_n1_mux_dataout	:	WIRE;
	l1_w2_n0_mux_dataout	:	WIRE;
	l1_w2_n1_mux_dataout	:	WIRE;
	l1_w3_n0_mux_dataout	:	WIRE;
	l1_w3_n1_mux_dataout	:	WIRE;
	l1_w4_n0_mux_dataout	:	WIRE;
	l1_w4_n1_mux_dataout	:	WIRE;
	l1_w5_n0_mux_dataout	:	WIRE;
	l1_w5_n1_mux_dataout	:	WIRE;
	l1_w6_n0_mux_dataout	:	WIRE;
	l1_w6_n1_mux_dataout	:	WIRE;
	l1_w7_n0_mux_dataout	:	WIRE;
	l1_w7_n1_mux_dataout	:	WIRE;
	l1_w8_n0_mux_dataout	:	WIRE;
	l1_w8_n1_mux_dataout	:	WIRE;
	l1_w9_n0_mux_dataout	:	WIRE;
	l1_w9_n1_mux_dataout	:	WIRE;
	l2_w0_n0_mux_dataout	:	WIRE;
	l2_w10_n0_mux_dataout	:	WIRE;
	l2_w11_n0_mux_dataout	:	WIRE;
	l2_w12_n0_mux_dataout	:	WIRE;
	l2_w13_n0_mux_dataout	:	WIRE;
	l2_w14_n0_mux_dataout	:	WIRE;
	l2_w15_n0_mux_dataout	:	WIRE;
	l2_w16_n0_mux_dataout	:	WIRE;
	l2_w17_n0_mux_dataout	:	WIRE;
	l2_w1_n0_mux_dataout	:	WIRE;
	l2_w2_n0_mux_dataout	:	WIRE;
	l2_w3_n0_mux_dataout	:	WIRE;
	l2_w4_n0_mux_dataout	:	WIRE;
	l2_w5_n0_mux_dataout	:	WIRE;
	l2_w6_n0_mux_dataout	:	WIRE;
	l2_w7_n0_mux_dataout	:	WIRE;
	l2_w8_n0_mux_dataout	:	WIRE;
	l2_w9_n0_mux_dataout	:	WIRE;
	data_wire[107..0]	: WIRE;
	sel_wire[1..0]	: WIRE;

BEGIN 
	l1_w0_n0_mux_dataout = sel_wire[0..0] & data_wire[18..18] # !(sel_wire[0..0]) & data_wire[0..0];
	l1_w0_n1_mux_dataout = sel_wire[0..0] & data_wire[54..54] # !(sel_wire[0..0]) & data_wire[36..36];
	l1_w10_n0_mux_dataout = sel_wire[0..0] & data_wire[28..28] # !(sel_wire[0..0]) & data_wire[10..10];
	l1_w10_n1_mux_dataout = sel_wire[0..0] & data_wire[64..64] # !(sel_wire[0..0]) & data_wire[46..46];
	l1_w11_n0_mux_dataout = sel_wire[0..0] & data_wire[29..29] # !(sel_wire[0..0]) & data_wire[11..11];
	l1_w11_n1_mux_dataout = sel_wire[0..0] & data_wire[65..65] # !(sel_wire[0..0]) & data_wire[47..47];
	l1_w12_n0_mux_dataout = sel_wire[0..0] & data_wire[30..30] # !(sel_wire[0..0]) & data_wire[12..12];
	l1_w12_n1_mux_dataout = sel_wire[0..0] & data_wire[66..66] # !(sel_wire[0..0]) & data_wire[48..48];
	l1_w13_n0_mux_dataout = sel_wire[0..0] & data_wire[31..31] # !(sel_wire[0..0]) & data_wire[13..13];
	l1_w13_n1_mux_dataout = sel_wire[0..0] & data_wire[67..67] # !(sel_wire[0..0]) & data_wire[49..49];
	l1_w14_n0_mux_dataout = sel_wire[0..0] & data_wire[32..32] # !(sel_wire[0..0]) & data_wire[14..14];
	l1_w14_n1_mux_dataout = sel_wire[0..0] & data_wire[68..68] # !(sel_wire[0..0]) & data_wire[50..50];
	l1_w15_n0_mux_dataout = sel_wire[0..0] & data_wire[33..33] # !(sel_wire[0..0]) & data_wire[15..15];
	l1_w15_n1_mux_dataout = sel_wire[0..0] & data_wire[69..69] # !(sel_wire[0..0]) & data_wire[51..51];
	l1_w16_n0_mux_dataout = sel_wire[0..0] & data_wire[34..34] # !(sel_wire[0..0]) & data_wire[16..16];
	l1_w16_n1_mux_dataout = sel_wire[0..0] & data_wire[70..70] # !(sel_wire[0..0]) & data_wire[52..52];
	l1_w17_n0_mux_dataout = sel_wire[0..0] & data_wire[35..35] # !(sel_wire[0..0]) & data_wire[17..17];
	l1_w17_n1_mux_dataout = sel_wire[0..0] & data_wire[71..71] # !(sel_wire[0..0]) & data_wire[53..53];
	l1_w1_n0_mux_dataout = sel_wire[0..0] & data_wire[19..19] # !(sel_wire[0..0]) & data_wire[1..1];
	l1_w1_n1_mux_dataout = sel_wire[0..0] & data_wire[55..55] # !(sel_wire[0..0]) & data_wire[37..37];
	l1_w2_n0_mux_dataout = sel_wire[0..0] & data_wire[20..20] # !(sel_wire[0..0]) & data_wire[2..2];
	l1_w2_n1_mux_dataout = sel_wire[0..0] & data_wire[56..56] # !(sel_wire[0..0]) & data_wire[38..38];
	l1_w3_n0_mux_dataout = sel_wire[0..0] & data_wire[21..21] # !(sel_wire[0..0]) & data_wire[3..3];
	l1_w3_n1_mux_dataout = sel_wire[0..0] & data_wire[57..57] # !(sel_wire[0..0]) & data_wire[39..39];
	l1_w4_n0_mux_dataout = sel_wire[0..0] & data_wire[22..22] # !(sel_wire[0..0]) & data_wire[4..4];
	l1_w4_n1_mux_dataout = sel_wire[0..0] & data_wire[58..58] # !(sel_wire[0..0]) & data_wire[40..40];
	l1_w5_n0_mux_dataout = sel_wire[0..0] & data_wire[23..23] # !(sel_wire[0..0]) & data_wire[5..5];
	l1_w5_n1_mux_dataout = sel_wire[0..0] & data_wire[59..59] # !(sel_wire[0..0]) & data_wire[41..41];
	l1_w6_n0_mux_dataout = sel_wire[0..0] & data_wire[24..24] # !(sel_wire[0..0]) & data_wire[6..6];
	l1_w6_n1_mux_dataout = sel_wire[0..0] & data_wire[60..60] # !(sel_wire[0..0]) & data_wire[42..42];
	l1_w7_n0_mux_dataout = sel_wire[0..0] & data_wire[25..25] # !(sel_wire[0..0]) & data_wire[7..7];
	l1_w7_n1_mux_dataout = sel_wire[0..0] & data_wire[61..61] # !(sel_wire[0..0]) & data_wire[43..43];
	l1_w8_n0_mux_dataout = sel_wire[0..0] & data_wire[26..26] # !(sel_wire[0..0]) & data_wire[8..8];
	l1_w8_n1_mux_dataout = sel_wire[0..0] & data_wire[62..62] # !(sel_wire[0..0]) & data_wire[44..44];
	l1_w9_n0_mux_dataout = sel_wire[0..0] & data_wire[27..27] # !(sel_wire[0..0]) & data_wire[9..9];
	l1_w9_n1_mux_dataout = sel_wire[0..0] & data_wire[63..63] # !(sel_wire[0..0]) & data_wire[45..45];
	l2_w0_n0_mux_dataout = sel_wire[1..1] & data_wire[73..73] # !(sel_wire[1..1]) & data_wire[72..72];
	l2_w10_n0_mux_dataout = sel_wire[1..1] & data_wire[93..93] # !(sel_wire[1..1]) & data_wire[92..92];
	l2_w11_n0_mux_dataout = sel_wire[1..1] & data_wire[95..95] # !(sel_wire[1..1]) & data_wire[94..94];
	l2_w12_n0_mux_dataout = sel_wire[1..1] & data_wire[97..97] # !(sel_wire[1..1]) & data_wire[96..96];
	l2_w13_n0_mux_dataout = sel_wire[1..1] & data_wire[99..99] # !(sel_wire[1..1]) & data_wire[98..98];
	l2_w14_n0_mux_dataout = sel_wire[1..1] & data_wire[101..101] # !(sel_wire[1..1]) & data_wire[100..100];
	l2_w15_n0_mux_dataout = sel_wire[1..1] & data_wire[103..103] # !(sel_wire[1..1]) & data_wire[102..102];
	l2_w16_n0_mux_dataout = sel_wire[1..1] & data_wire[105..105] # !(sel_wire[1..1]) & data_wire[104..104];
	l2_w17_n0_mux_dataout = sel_wire[1..1] & data_wire[107..107] # !(sel_wire[1..1]) & data_wire[106..106];
	l2_w1_n0_mux_dataout = sel_wire[1..1] & data_wire[75..75] # !(sel_wire[1..1]) & data_wire[74..74];
	l2_w2_n0_mux_dataout = sel_wire[1..1] & data_wire[77..77] # !(sel_wire[1..1]) & data_wire[76..76];
	l2_w3_n0_mux_dataout = sel_wire[1..1] & data_wire[79..79] # !(sel_wire[1..1]) & data_wire[78..78];
	l2_w4_n0_mux_dataout = sel_wire[1..1] & data_wire[81..81] # !(sel_wire[1..1]) & data_wire[80..80];
	l2_w5_n0_mux_dataout = sel_wire[1..1] & data_wire[83..83] # !(sel_wire[1..1]) & data_wire[82..82];
	l2_w6_n0_mux_dataout = sel_wire[1..1] & data_wire[85..85] # !(sel_wire[1..1]) & data_wire[84..84];
	l2_w7_n0_mux_dataout = sel_wire[1..1] & data_wire[87..87] # !(sel_wire[1..1]) & data_wire[86..86];
	l2_w8_n0_mux_dataout = sel_wire[1..1] & data_wire[89..89] # !(sel_wire[1..1]) & data_wire[88..88];
	l2_w9_n0_mux_dataout = sel_wire[1..1] & data_wire[91..91] # !(sel_wire[1..1]) & data_wire[90..90];
	data_wire[] = ( l1_w17_n1_mux_dataout, l1_w17_n0_mux_dataout, l1_w16_n1_mux_dataout, l1_w16_n0_mux_dataout, l1_w15_n1_mux_dataout, l1_w15_n0_mux_dataout, l1_w14_n1_mux_dataout, l1_w14_n0_mux_dataout, l1_w13_n1_mux_dataout, l1_w13_n0_mux_dataout, l1_w12_n1_mux_dataout, l1_w12_n0_mux_dataout, l1_w11_n1_mux_dataout, l1_w11_n0_mux_dataout, l1_w10_n1_mux_dataout, l1_w10_n0_mux_dataout, l1_w9_n1_mux_dataout, l1_w9_n0_mux_dataout, l1_w8_n1_mux_dataout, l1_w8_n0_mux_dataout, l1_w7_n1_mux_dataout, l1_w7_n0_mux_dataout, l1_w6_n1_mux_dataout, l1_w6_n0_mux_dataout, l1_w5_n1_mux_dataout, l1_w5_n0_mux_dataout, l1_w4_n1_mux_dataout, l1_w4_n0_mux_dataout, l1_w3_n1_mux_dataout, l1_w3_n0_mux_dataout, l1_w2_n1_mux_dataout, l1_w2_n0_mux_dataout, l1_w1_n1_mux_dataout, l1_w1_n0_mux_dataout, l1_w0_n1_mux_dataout, l1_w0_n0_mux_dataout, data[]);
	result[] = ( l2_w17_n0_mux_dataout, l2_w16_n0_mux_dataout, l2_w15_n0_mux_dataout, l2_w14_n0_mux_dataout, l2_w13_n0_mux_dataout, l2_w12_n0_mux_dataout, l2_w11_n0_mux_dataout, l2_w10_n0_mux_dataout, l2_w9_n0_mux_dataout, l2_w8_n0_mux_dataout, l2_w7_n0_mux_dataout, l2_w6_n0_mux_dataout, l2_w5_n0_mux_dataout, l2_w4_n0_mux_dataout, l2_w3_n0_mux_dataout, l2_w2_n0_mux_dataout, l2_w1_n0_mux_dataout, l2_w0_n0_mux_dataout);
	sel_wire[] = ( sel[1..0]);
END;
--VALID FILE