cntr_788.tdf

基于SIIGX的PCIe的Kit

--lpm_counter DEVICE_FAMILY="Stratix II" lpm_modulus=18 lpm_width=5 aclr clk_en(vcc) clock q
--VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:07:00:11:16:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_counter 2005:02:02:04:37:10:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_mgl 2005:03:28:10:52:10:SJ cbx_stratix 2005:03:14:17:09:02:SJ cbx_stratixii 2004:12:22:13:27:12:SJ  VERSION_END


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--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files any of the foregoing 
--  (including device programming or simulation files), and any 
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--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
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FUNCTION stratixii_lcell_comb (cin, dataa, datab, datac, datad, datae, dataf, datag, sharein)
WITH ( 	EXTENDED_LUT,	LUT_MASK,	SHARED_ARITH) 
RETURNS ( combout, cout, shareout, sumout);
FUNCTION stratixii_lcell_ff (aclr, adatasdata, aload, clk, datain, ena, sclr, sload)
RETURNS ( regout);

--synthesis_resources = lut 9 reg 5 
SUBDESIGN cntr_788
( 
	aclr	:	input;
	clk_en	:	input;
	clock	:	input;
	q[4..0]	:	output;
) 
VARIABLE
	cmpr2_aeb_int	:	WIRE;
	cmpr2_aeb	:	WIRE;
	cmpr2_dataa[4..0]	:	WIRE;
	cmpr2_datab[4..0]	:	WIRE;
	counter_comb_bita0 : stratixii_lcell_comb
		WITH (
			EXTENDED_LUT = "OFF",
			LUT_MASK = "000000000000AAAA",
			SHARED_ARITH = "OFF"
		);
	counter_comb_bita1 : stratixii_lcell_comb
		WITH (
			EXTENDED_LUT = "OFF",
			LUT_MASK = "0000555500003333",
			SHARED_ARITH = "OFF"
		);
	counter_comb_bita2 : stratixii_lcell_comb
		WITH (
			EXTENDED_LUT = "OFF",
			LUT_MASK = "0000555500003333",
			SHARED_ARITH = "OFF"
		);
	counter_comb_bita3 : stratixii_lcell_comb
		WITH (
			EXTENDED_LUT = "OFF",
			LUT_MASK = "0000555500003333",
			SHARED_ARITH = "OFF"
		);
	counter_comb_bita4 : stratixii_lcell_comb
		WITH (
			EXTENDED_LUT = "OFF",
			LUT_MASK = "0000555500003333",
			SHARED_ARITH = "OFF"
		);
	counter_reg_bit1a[4..0] : stratixii_lcell_ff;
	a_val[4..0]	: WIRE;
	aclr_actual	: WIRE;
	cnt_en	: NODE;
	compare_result	: WIRE;
	cout_actual	: WIRE;
	data[4..0]	: NODE;
	external_cin	: WIRE;
	lsb_cin	: WIRE;
	modulus_bus[4..0]	: WIRE;
	modulus_trigger	: WIRE;
	s_val[4..0]	: WIRE;
	safe_q[4..0]	: WIRE;
	sclr	: NODE;
	sload	: NODE;
	sset	: NODE;
	time_to_clear	: WIRE;
	updown_dir	: WIRE;
	updown_lsb	: WIRE;
	updown_other_bits	: WIRE;

BEGIN 
	IF (cmpr2_dataa[] == cmpr2_datab[]) THEN
		cmpr2_aeb_int = VCC;
	ELSE
		cmpr2_aeb_int = GND;
	END IF;
	cmpr2_aeb = cmpr2_aeb_int;
	cmpr2_dataa[] = safe_q[];
	cmpr2_datab[] = modulus_bus[];
	counter_comb_bita[0].cin = lsb_cin;
	counter_comb_bita[1].cin = counter_comb_bita[0].cout;
	counter_comb_bita[2].cin = counter_comb_bita[1].cout;
	counter_comb_bita[3].cin = counter_comb_bita[2].cout;
	counter_comb_bita[4].cin = counter_comb_bita[3].cout;
	counter_comb_bita[0].dataa = counter_reg_bit1a[0].regout;
	counter_comb_bita[1].dataa = counter_reg_bit1a[1].regout;
	counter_comb_bita[2].dataa = counter_reg_bit1a[2].regout;
	counter_comb_bita[3].dataa = counter_reg_bit1a[3].regout;
	counter_comb_bita[4].dataa = counter_reg_bit1a[4].regout;
	counter_comb_bita[0].datab = updown_lsb;
	counter_comb_bita[1].datab = updown_other_bits;
	counter_comb_bita[2].datab = updown_other_bits;
	counter_comb_bita[3].datab = updown_other_bits;
	counter_comb_bita[4].datab = updown_other_bits;
	counter_reg_bit1a[].aclr = aclr_actual;
	counter_reg_bit1a[].adatasdata = ((sset & s_val[]) # ((! sset) & ((sload & data[]) # (((! sload) & modulus_bus[]) & (! updown_dir)))));
	counter_reg_bit1a[].clk = clock;
	counter_reg_bit1a[0].datain = counter_comb_bita[0].sumout;
	counter_reg_bit1a[1].datain = counter_comb_bita[1].sumout;
	counter_reg_bit1a[2].datain = counter_comb_bita[2].sumout;
	counter_reg_bit1a[3].datain = counter_comb_bita[3].sumout;
	counter_reg_bit1a[4].datain = counter_comb_bita[4].sumout;
	counter_reg_bit1a[].ena = (clk_en & (((cnt_en # sclr) # sset) # sload));
	counter_reg_bit1a[].sclr = sclr;
	counter_reg_bit1a[].sload = ((sset # sload) # modulus_trigger);
	a_val[] = B"11111";
	aclr_actual = aclr;
	cnt_en = VCC;
	compare_result = cmpr2_aeb;
	cout_actual = (((! counter_comb_bita[4].cout) $ updown_other_bits) # (time_to_clear & updown_dir));
	data[] = GND;
	external_cin = B"1";
	lsb_cin = B"0";
	modulus_bus[] = B"10001";
	modulus_trigger = cout_actual;
	q[] = safe_q[];
	s_val[] = B"11111";
	safe_q[] = counter_reg_bit1a[].regout;
	sclr = GND;
	sload = GND;
	sset = GND;
	time_to_clear = compare_result;
	updown_dir = B"1";
	updown_lsb = updown_dir;
	updown_other_bits = ((! external_cin) # updown_dir);
END;
--VALID FILE