altsyncram_4s82.tdf

来自「基于SIIGX的PCIe的Kit」· TDF 代码 · 共 1,810 行 · 第 1/5 页

TDF
1,810 行
字号
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			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 8192,
			PORT_B_FIRST_BIT_NUMBER = 15,
			PORT_B_LAST_ADDRESS = 12287,
			PORT_B_LOGICAL_RAM_DEPTH = 16384,
			PORT_B_LOGICAL_RAM_WIDTH = 18,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "M4K"
		);
	ram_block1a52 : stratixii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 8192,
			PORT_A_FIRST_BIT_NUMBER = 16,
			PORT_A_LAST_ADDRESS = 12287,
			PORT_A_LOGICAL_RAM_DEPTH = 16384,
			PORT_A_LOGICAL_RAM_WIDTH = 18,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 8192,
			PORT_B_FIRST_BIT_NUMBER = 16,
			PORT_B_LAST_ADDRESS = 12287,
			PORT_B_LOGICAL_RAM_DEPTH = 16384,
			PORT_B_LOGICAL_RAM_WIDTH = 18,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "M4K"
		);
	ram_block1a53 : stratixii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 8192,
			PORT_A_FIRST_BIT_NUMBER = 17,
			PORT_A_LAST_ADDRESS = 12287,
			PORT_A_LOGICAL_RAM_DEPTH = 16384,
			PORT_A_LOGICAL_RAM_WIDTH = 18,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 8192,
			PORT_B_FIRST_BIT_NUMBER = 17,
			PORT_B_LAST_ADDRESS = 12287,
			PORT_B_LOGICAL_RAM_DEPTH = 16384,
			PORT_B_LOGICAL_RAM_WIDTH = 18,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "M4K"
		);
	ram_block1a54 : stratixii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 12288,
			PORT_A_FIRST_BIT_NUMBER = 0,
			PORT_A_LAST_ADDRESS = 16383,
			PORT_A_LOGICAL_RAM_DEPTH = 16384,
			PORT_A_LOGICAL_RAM_WIDTH = 18,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 12288,
			PORT_B_FIRST_BIT_NUMBER = 0,
			PORT_B_LAST_ADDRESS = 16383,
			PORT_B_LOGICAL_RAM_DEPTH = 16384,
			PORT_B_LOGICAL_RAM_WIDTH = 18,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "M4K"
		);
	ram_block1a55 : stratixii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 12288,
			PORT_A_FIRST_BIT_NUMBER = 1,
			PORT_A_LAST_ADDRESS = 16383,
			PORT_A_LOGICAL_RAM_DEPTH = 16384,
			PORT_A_LOGICAL_RAM_WIDTH = 18,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 12288,
			PORT_B_FIRST_BIT_NUMBER = 1,
			PORT_B_LAST_ADDRESS = 16383,
			PORT_B_LOGICAL_RAM_DEPTH = 16384,
			PORT_B_LOGICAL_RAM_WIDTH = 18,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "M4K"
		);
	ram_block1a56 : stratixii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 12288,
			PORT_A_FIRST_BIT_NUMBER = 2,
			PORT_A_LAST_ADDRESS = 16383,
			PORT_A_LOGICAL_RAM_DEPTH = 16384,
			PORT_A_LOGICAL_RAM_WIDTH = 18,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 12288,
			PORT_B_FIRST_BIT_NUMBER = 2,
			PORT_B_LAST_ADDRESS = 16383,
			PORT_B_LOGICAL_RAM_DEPTH = 16384,
			PORT_B_LOGICAL_RAM_WIDTH = 18,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "M4K"
		);
	ram_block1a57 : stratixii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 12288,
			PORT_A_FIRST_BIT_NUMBER = 3,
			PORT_A_LAST_ADDRESS = 16383,
			PORT_A_LOGICAL_RAM_DEPTH = 16384,
			PORT_A_LOGICAL_RAM_WIDTH = 18,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 12288,
			PORT_B_FIRST_BIT_NUMBER = 3,
			PORT_B_LAST_ADDRESS = 16383,
			PORT_B_LOGICAL_RAM_DEPTH = 16384,
			PORT_B_LOGICAL_RAM_WIDTH = 18,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "M4K"
		);
	ram_block1a58 : stratixii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 12288,
			PORT_A_FIRST_BIT_NUMBER = 4,
			PORT_A_LAST_ADDRESS = 16383,
			PORT_A_LOGICAL_RAM_DEPTH = 16384,
			PORT_A_LOGICAL_RAM_WIDTH = 18,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 12288,
			PORT_B_FIRST_BIT_NUMBER = 4,
			PORT_B_LAST_ADDRESS = 16383,
			PORT_B_LOGICAL_RAM_DEPTH = 16384,
			PORT_B_LOGICAL_RAM_WIDTH = 18,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "M4K"
		);
	ram_block1a59 : stratixii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 12288,
			PORT_A_FIRST_BIT_NUMBER = 5,
			PORT_A_LAST_ADDRESS = 16383,
			PORT_A_LOGICAL_RAM_DEPTH = 16384,
			PORT_A_LOGICAL_RAM_WIDTH = 18,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 12288,
			PORT_B_FIRST_BIT_NUMBER = 5,
			PORT_B_LAST_ADDRESS = 16383,
			PORT_B_LOGICAL_RAM_DEPTH = 16384,
			PORT_B_LOGICAL_RAM_WIDTH = 18,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "M4K"
		);
	ram_block1a60 : stratixii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 12288,
			PORT_A_FIRST_BIT_NUMBER = 6,
			PORT_A_LAST_ADDRESS = 16383,
			PORT_A_LOGICAL_RAM_DEPTH = 16384,
			PORT_A_LOGICAL_RAM_WIDTH = 18,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 12288,
			PORT_B_FIRST_BIT_NUMBER = 6,
			PORT_B_LAST_ADDRESS = 16383,
			PORT_B_LOGICAL_RAM_DEPTH = 16384,
			PORT_B_LOGICAL_RAM_WIDTH = 18,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "M4K"
		);
	ram_block1a61 : stratixii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 12288,
			PORT_A_FIRST_BIT_NUMBER = 7,
			PORT_A_LAST_ADDRESS = 16383,
			PORT_A_LOGICAL_RAM_DEPTH = 16384,
			PORT_A_LOGICAL_RAM_WIDTH = 18,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 12288,
			PORT_B_FIRST_BIT_NUMBER = 7,
			PORT_B_LAST_ADDRESS = 16383,
			PORT_B_LOGICAL_RAM_DEPTH = 16384,
			PORT_B_LOGICAL_RAM_WIDTH = 18,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "M4K"
		);
	ram_block1a62 : stratixii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 12288,
			PORT_A_FIRST_BIT_NUMBER = 8,
			PORT_A_LAST_ADDRESS = 16383,
			PORT_A_LOGICAL_RAM_DEPTH = 16384,
			PORT_A_LOGICAL_RAM_WIDTH = 18,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 12288,
			PORT_B_FIRST_BIT_NUMBER = 8,
			PORT_B_LAST_ADDRESS = 16383,
			PORT_B_LOGICAL_RAM_DEPTH = 16384,
			PORT_B_LOGICAL_RAM_WIDTH = 18,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "M4K"
		);
	ram_block1a63 : stratixii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 12288,
			PORT_A_FIRST_BIT_NUMBER = 9,
			PORT_A_LAST_ADDRESS = 16383,
			PORT_A_LOGICAL_RAM_DEPTH = 16384,
			PORT_A_LOGICAL_RAM_WIDTH = 18,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 12288,
			PORT_B_FIRST_BIT_NUMBER = 9,
			PORT_B_LAST_ADDRESS = 16383,
			PORT_B_LOGICAL_RAM_DEPTH = 16384,
			PORT_B_LOGICAL_RAM_WIDTH = 18,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "M4K"
		);
	ram_block1a64 : stratixii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 12288,
			PORT_A_FIRST_BIT_NUMBER = 10,
			PORT_A_LAST_ADDRESS = 16383,
			PORT_A_LOGICAL_RAM_DEPTH = 16384,
			PORT_A_LOGICAL_RAM_WIDTH = 18,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 12288,
			PORT_B_FIRST_BIT_NUMBER = 10,
			PORT_B_LAST_ADDRESS = 16383,
			PORT_B_LOGICAL_RAM_DEPTH = 16384,
			PORT_B_LOGICAL_RAM_WIDTH = 18,
			PORT_B_READ_ENABLE_WRITE_ENA
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altsyncram_4s82.tdf - 源码说明

本页面展示了「基于SIIGX的PCIe的Kit」中的 altsyncram_4s82.tdf 源码文件，采用 TDF 编程语言编写，共 1,810 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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