📄 thermal_bak.v
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/* write/read for MAX1619 Temp_sensor */
/* write Temperature Limits to MAX1619 */
/* Temp_high_Limit = 45C (Fan ON) Temp_Hyst = 40C (Fan Off)*/
/* Read data from MAX1619 and display to seven segment */
module thermal(clock_in, reset, smb_clock, smb_data, data_out,start);
output smb_clock;
output [7:0] data_out;
//output [3:0] remain_out;
inout smb_data;
input clock_in, reset;
input start;
//internal data structures
reg clock;
wire smb_data_in;
reg [7:0] data_read;
reg [7:0] data_o;
reg [8:0] smb_data_out;
reg [4:0] state;
//reg [3:0] count;
reg temp;
reg data_control;
reg clock_control;
reg read;
integer count;
parameter address = 7'b0011000;
parameter thermal_reg = 8'h01;
parameter state_zero = 5'b00000; //0
parameter state_one = 5'b00001; //1
parameter state_two = 5'b00010; //2
parameter state_three = 5'b00011; //3
parameter state_four = 5'b00100; //4
parameter state_five = 5'b00101; //5
parameter state_six = 5'b00110; //6
parameter state_seven = 5'b00111; //7
parameter state_eight = 5'b01000; //8
parameter state_nine = 5'b01001; //9
parameter state_ten = 5'b01010; //10
parameter state_eleven = 5'b01011; //11
parameter state_twelve = 5'b01100; //12
parameter state_w_zero = 5'b01101; //13
parameter state_w_one = 5'b01110; //14
parameter state_w_two = 5'b01111; //15
parameter state_w_three = 5'b10000; //16
parameter state_w_four = 5'b10001; //17
parameter state_w_five = 5'b10010; //18
parameter state_w_six = 5'b10011; //19
parameter state_w_seven = 5'b10100; //20
parameter state_w_eight = 5'b10101; //21
parameter state_w_nine = 5'b10110; //22
parameter state_w_ten = 5'b10111; //23
parameter state_w_eleven = 5'b11000; //24
parameter state_w_twelve = 5'b11001; //25
assign smb_data_in = smb_data;
assign data_out = data_o;
//assign quot_out = data_o div 4'b0101;
//assign remain_out = data_o mod 4'b0101;
assign smb_data = data_control ? smb_data_out[8]:1'bz;
assign smb_clock = ~clock_control ? ~clock_in:1'bz;
//bufif1 buf1(smb_clock, ~clock_in, clock_control);
//bufif1 buf2(smb_data, smb_data_out[8], data_control);
// Synchronize the module outputs.
always @ (posedge clock_in)
begin
// if (~start)begin
// smb_data_out <= address << 1;
// count <= 8;
// smb_data_out[0] <= 1'b0;
// state <= state_zero;
// end
// else begin
/*Write_Temperature_sense_start_code*/
/* write Temperature Limits to MAX1619 */
/* Temp_high_Limit = 45C (Fan ON) Temp_Hyst = 40C (Fan Off)*/
case (state)
state_w_zero: //write start
begin
clock_control <= 1;
data_control <= 0;
smb_data_out <= address << 1;
count <= 8;
smb_data_out[0] <= 1'b0;
if (~start)
state <= state_w_one;
else
state <= state_w_zero;
end
state_w_one: //write start bit
begin
clock_control <= 1;
data_control <= 1;
// clock = 1'b0;
state <= state_w_two;
end
state_w_two: //write slave address to Max1619 (7bits) 0011000
begin
clock_control <= 0;
data_control <= 1;
clock = clock_in;
smb_data_out[8] <= smb_data_out[count-1]; //smb_data_out = 7bits 0011000 and wr bit
// smb_data_out[7] <= smb_data_out[6];
// smb_data_out[6] <= smb_data_out[5];
// smb_data_out[5] <= smb_data_out[4];
// smb_data_out[4] <= smb_data_out[3];
// smb_data_out[3] <= smb_data_out[2];
// smb_data_out[2] <= smb_data_out[1];
// smb_data_out[1] <= smb_data_out[0];
count <= count -1;
if (count == 0)
begin
// clock_control <= 1;
data_control = 0;
count <= 8;
state <= state_w_three;
end
else
state <= state_w_two;
end
state_w_three: //waiting for ack
begin
clock_control <= 0;
data_control <= 0;
smb_data_out <= thermal_reg; //thermal reg = 8'h01
// count <= 8;
if (~smb_data_in)
begin
clock_control <= 0;
data_control <= 1;
smb_data_out[8] <= smb_data_out[count-1];
count <= count - 1;
state <= state_w_five;
end
else
state <= state_w_three;
end
state_w_four: //acknowledge should receive from slave MAX1619
begin
clock_control <= 1;
data_control <= 1;
// smb_data_out[0] <= 1'b1;
clock = 1'b0;
state <= state_w_five;
end
state_w_five: //write command to slave Max1619
begin
clock_control <= 0;
data_control <= 1;
clock = clock_in;
smb_data_out[8] <= smb_data_out[count-1];
// smb_data_out[7] <= smb_data_out[6];
// smb_data_out[6] <= smb_data_out[5];
// smb_data_out[5] <= smb_data_out[4];
// smb_data_out[4] <= smb_data_out[3];
// smb_data_out[3] <= smb_data_out[2];
// smb_data_out[2] <= smb_data_out[1];
// smb_data_out[1] <= smb_data_out[0];
count <= count - 1;
if (count == 0)
begin
// clock_control <= 1;
state <= state_w_six;
data_control <= 0;
end
else
state <= state_w_five;
end
state_w_six: //waiting for acknowdlege from slave
begin
// clock_control <= 1;
data_control <= 0;
smb_data_out <= address << 1;
smb_data_out[0] <= 1'b1;
count <= 8;
if (~smb_data_in) //once ack receive go to state_seven
begin
clock_control <= 1;
state <= state_w_seven;
end
else
state <= state_w_six;
end
state_w_seven: //tri-state
begin
clock_control <= 1;
data_control <= 0;
state <= state_w_eight;
end
state_w_eight: //tri-state
begin
clock_control <= 1;
data_control <= 1;
clock = 1'b0;
state <= state_w_nine;
end
state_w_nine: //write data to slave Max1619
begin
clock_control <= 0;
data_control <= 1;
clock = clock_in;
smb_data_out[8] <= smb_data_out[count-1]; //data = 2Dh 0010 1101
// smb_data_out[7] <= smb_data_out[6];
// smb_data_out[6] <= smb_data_out[5];
// smb_data_out[5] <= smb_data_out[4];
// smb_data_out[4] <= smb_data_out[3];
// smb_data_out[3] <= smb_data_out[2];
// smb_data_out[2] <= smb_data_out[1];
// smb_data_out[1] <= smb_data_out[0];
count = count -1;
if (count == 0)
state <= state_w_ten;
else
state <= state_w_nine;
end
state_w_ten: //receive acknowledge from slave Max1619
begin
// clock_control <= 1;
data_control <= 0;
// smb_data_out <= address << 1;
count <= 8;
if (~smb_data_in)
begin
clock_control <= 1;
state <= state_w_twelve;
end
else
state <= state_w_ten;
end
/* state_w_eleven:
begin
clock_control <= 0;
data_control <= 0;
data_read[0] <= smb_data_in;
count <= count - 1;
if (count == 0)
begin
count <= 8;
smb_data_out <= address << 1;
smb_data_out[0] <= 1'b1;
data_o <= data_read;
clock_control <= 0;
state <= state_w_twelve;
end
else
begin
data_read[7] <= data_read[6];
data_read[6] <= data_read[5];
data_read[5] <= data_read[4];
data_read[4] <= data_read[3];
data_read[3] <= data_read[2];
data_read[2] <= data_read[1];
data_read[1] <= data_read[0];
state <= state_w_eleven;
end
end
*/
state_w_twelve: //stop bit
begin
clock_control <= 1;
data_control <= 0;
count <= count - 1;
if (count == 0)
begin
count <= 8;
// smb_data_out <= address << 1;
state <= state_w_seven;
end
else
begin
state <= state_w_twelve;
end
end
/*Read_Temperature_sense_start_code*/
state_zero:
begin
clock_control <= 1;
data_control <= 0;
smb_data_out <= address << 1;
count <= 8;
smb_data_out[0] <= 1'b0;
// if (~start)
state <= state_w_one;
// else
// state <= state_zero;
end
state_one:
begin
clock_control <= 1;
data_control <= 1;
// clock = 1'b0;
state <= state_w_two;
end
state_two:
begin
clock_control <= 0;
data_control <= 1;
clock = clock_in;
smb_data_out[8] <= smb_data_out[count-1];
// smb_data_out[7] <= smb_data_out[6];
// smb_data_out[6] <= smb_data_out[5];
// smb_data_out[5] <= smb_data_out[4];
// smb_data_out[4] <= smb_data_out[3];
// smb_data_out[3] <= smb_data_out[2];
// smb_data_out[2] <= smb_data_out[1];
// smb_data_out[1] <= smb_data_out[0];
count <= count -1;
if (count == 0)
begin
// clock_control <= 1;
data_control = 0;
count <= 8;
state <= state_w_three;
end
else
state <= state_w_two;
end
state_three:
begin
clock_control <= 0;
data_control <= 0;
smb_data_out <= thermal_reg;
// count <= 8;
if (~smb_data_in)
begin
clock_control <= 0;
data_control <= 1;
smb_data_out[8] <= smb_data_out[count-1];
count <= count - 1;
state <= state_w_five;
end
else
state <= state_w_three;
end
state_four:
begin
clock_control <= 1;
data_control <= 1;
// smb_data_out[0] <= 1'b1;
clock = 1'b0;
state <= state_w_five;
end
state_five:
begin
clock_control <= 0;
data_control <= 1;
clock = clock_in;
smb_data_out[8] <= smb_data_out[count-1];
// smb_data_out[7] <= smb_data_out[6];
// smb_data_out[6] <= smb_data_out[5];
// smb_data_out[5] <= smb_data_out[4];
// smb_data_out[4] <= smb_data_out[3];
// smb_data_out[3] <= smb_data_out[2];
// smb_data_out[2] <= smb_data_out[1];
// smb_data_out[1] <= smb_data_out[0];
count <= count - 1;
if (count == 0)
begin
// clock_control <= 1;
state <= state_six;
data_control <= 0;
end
else
state <= state_five;
end
state_six:
begin
// clock_control <= 1;
data_control <= 0;
smb_data_out <= address << 1;
smb_data_out[0] <= 1'b1;
count <= 8;
if (~smb_data_in)
begin
clock_control <= 1;
state <= state_w_seven;
end
else
state <= state_w_six;
end
state_seven:
begin
clock_control <= 1;
data_control <= 0;
state <= state_w_eight;
end
state_eight:
begin
clock_control <= 1;
data_control <= 1;
clock = 1'b0;
state <= state_w_nine;
end
state_nine:
begin
clock_control <= 0;
data_control <= 1;
clock = clock_in;
smb_data_out[8] <= smb_data_out[count-1];
// smb_data_out[7] <= smb_data_out[6];
// smb_data_out[6] <= smb_data_out[5];
// smb_data_out[5] <= smb_data_out[4];
// smb_data_out[4] <= smb_data_out[3];
// smb_data_out[3] <= smb_data_out[2];
// smb_data_out[2] <= smb_data_out[1];
// smb_data_out[1] <= smb_data_out[0];
count = count -1;
if (count == 0)
state <= state_w_ten;
else
state <= state_w_nine;
end
state_ten:
begin
// clock_control <= 1;
data_control <= 0;
// smb_data_out <= address << 1;
count <= 8;
if (~smb_data_in) begin
clock_control <= 1;
state <= state_w_eleven;
end
else
state <= state_w_ten;
end
state_eleven:
begin
clock_control <= 0;
data_control <= 0;
data_read[0] <= smb_data_in;
count <= count - 1;
if (count == 0) begin
count <= 8;
smb_data_out <= address << 1;
smb_data_out[0] <= 1'b1;
data_o <= data_read;
clock_control <= 0;
state <= state_w_twelve;
end
else begin
data_read[7] <= data_read[6];
data_read[6] <= data_read[5];
data_read[5] <= data_read[4];
data_read[4] <= data_read[3];
data_read[3] <= data_read[2];
data_read[2] <= data_read[1];
data_read[1] <= data_read[0];
state <= state_w_eleven;
end
end
state_twelve:
begin
clock_control <= 1;
data_control <= 0;
count <= count - 1;
if (count == 0)
begin
count <= 8;
// smb_data_out <= address << 1;
state <= state_w_seven;
end
else begin
state <= state_w_twelve;
end
end
default: state <= state_w_zero;
endcase
// end
end
endmodule
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