thermal_top.tan.rpt

基于SIIGX的PCIe的Kit

; Worst-case tco               ; N/A   ; None          ; 12.073 ns                        ; thermal:b2v_inst3|smb_data_out[8]                                                                                                                         ; smb_data                               ; clk        ; --       ; 0            ;
; Worst-case th                ; N/A   ; None          ; 1.154 ns                         ; smb_data                                                                                                                                                  ; thermal:b2v_inst3|state.state_w_ten    ; --         ; clk      ; 0            ;
; Worst-case Minimum tco       ; N/A   ; None          ; 6.735 ns                         ; lpm_counter_10bit:b2v_inst09|lpm_counter:lpm_counter_component|cntr_7vh:auto_generated|safe_q[9]                                                          ; dig_b                                  ; clk        ; --       ; 0            ;
; Clock Setup: 'clk'           ; N/A   ; None          ; 165.26 MHz ( period = 6.051 ns ) ; divide_by_10:b2v_inst04|lpm_divide:lpm_divide_component|lpm_divide_jqt:auto_generated|sign_div_unsign_s5i:divider|alt_u_div_ksf:divider|DFFDenominator[7] ; led7seg_driver:b2v_inst08|count_reg[1] ; clk        ; clk      ; 0            ;
; Total number of failed paths ;       ;               ;                                  ;                                                                                                                                                           ;                                        ;            ;          ; 0            ;
+------------------------------+-------+---------------+----------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP2SGX90FF1508C3   ;      ;    ;             ;
; Timing Models                                         ; Preliminary        ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; On                 ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk'                                                                                                                                                                                                                                                                                                                                                                                             ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+