led7seg_driver.v

来自「基于SIIGX的PCIe的Kit」· Verilog 代码 · 共 105 行

module led7seg_driver (
		       clk,
		       reset_n,
		       count,
		       dp1_n,
		       dig_1_a,
		       dig_1_b,
		       dig_1_c,
		       dig_1_d,
		       dig_1_e,
		       dig_1_f,
		       dig_1_g,
		       dig_1_dp,
		       );

   input [3:0] count;
   input       clk;
   input       reset_n;
   input       dp1_n;

   output      dig_1_a;
   output      dig_1_b;
   output      dig_1_c;
   output      dig_1_d;
   output      dig_1_e;
   output      dig_1_f;
   output      dig_1_g;
   output      dig_1_dp;

   reg 	       dig_1_a;
   reg 	       dig_1_b;
   reg 	       dig_1_c;
   reg 	       dig_1_d;
   reg 	       dig_1_e;
   reg 	       dig_1_f;
   reg 	       dig_1_g;
   reg 	       dig_1_dp;

   reg 	       count_one;
   reg 	       count_two;
   reg 	       count_three;
   reg 	       count_four;
   reg 	       count_five;
   reg 	       count_six;
   reg 	       count_seven;
   reg         count_eight;
   reg 	       count_nine;
   reg 	       count_zero;
   reg         count_a;
   reg         count_b;
   reg         count_c;
   reg         count_d;
   reg         count_e;
   reg         count_f;

   reg [3:0]   count_reg;
 
   always@(posedge clk)
      begin
	 if (!reset_n)
	    begin
	       dig_1_a <= 0;
	       dig_1_b <= 0;
	       dig_1_c <= 0;
	       dig_1_d <= 0;
	       dig_1_e <= 0;
	       dig_1_f <= 0;
	       dig_1_g <= 1;
	       dig_1_dp <= 1;
	    end
	 else
	   begin
	      dig_1_dp <= dp1_n;
	      
	      count_reg <= count;
	      	      
              count_zero = !count_reg[3] & !count_reg[2] & !count_reg[1] & !count_reg[0];
	      count_one = !count_reg[3] & !count_reg[2] & !count_reg[1] & count_reg[0];
              count_two = !count_reg[3] & !count_reg[2] & count_reg[1] & !count_reg[0];
              count_three = !count_reg[3] & !count_reg[2] & count_reg[1] & count_reg[0];
              count_four = !count_reg[3] & count_reg[2] & !count_reg[1] & !count_reg[0];
              count_five = !count_reg[3] & count_reg[2] & !count_reg[1] & count_reg[0];
              count_six = !count_reg[3] & count_reg[2] & count_reg[1] & !count_reg[0];
              count_seven = !count_reg[3] & count_reg[2] & count_reg[1] & count_reg[0];
	      count_eight = count_reg[3] & !count_reg[2] & !count_reg[1] & count_reg[0];
              count_nine = count_reg[3] & !count_reg[2] & !count_reg[1] & count_reg[0];
              count_a = count_reg[3] & !count_reg[2] & count_reg[1] & !count_reg[0];
              count_b = count_reg[3] & !count_reg[2] & count_reg[1] & count_reg[0];
              count_c = count_reg[3] & count_reg[2] & !count_reg[1] & !count_reg[0];
              count_d = count_reg[3] & count_reg[2] & !count_reg[1] & count_reg[0];
              count_e = count_reg[3] & count_reg[2] & count_reg[1] & !count_reg[0];
              count_f = count_reg[3] & count_reg[2] & count_reg[1] & count_reg[0];
	      
	      dig_1_a <= (count_one | count_four | count_b | count_c | count_d);
	      dig_1_b <= (count_five | count_six | count_b | count_c | count_e | count_f);
	      dig_1_c <= (count_two | count_c | count_e | count_f);
	      dig_1_d <= (count_one | count_four | count_seven | count_a | count_f);
	      dig_1_e <= (count_one | count_three | count_four | count_five | count_seven | count_nine);
	      dig_1_f <= (count_one | count_two | count_three | count_seven | count_c | count_d);
	      dig_1_g <= (count_one | count_seven | count_zero);
	   end
      end
endmodule