thermal_top.qsf

基于SIIGX的PCIe的Kit

# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic       
# functions, and any output files any of the foregoing           
# (including device programming or simulation files), and any    
# associated documentation or information are expressly subject  
# to the terms and conditions of the Altera Program License      
# Subscription Agreement, Altera MegaCore Function License       
# Agreement, or other applicable license agreement, including,   
# without limitation, that your use is for the sole purpose of   
# programming logic devices manufactured by Altera and sold by   
# Altera or its authorized distributors.  Please refer to the    
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		thermal_top_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "4.1 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:15:34  SEPTEMBER 19, 2004"
set_global_assignment -name LAST_QUARTUS_VERSION 7.0

# Pin & Location Assignments
# ==========================
set_location_assignment PIN_AU17 -to smb_data
set_location_assignment PIN_AV21 -to smb_clk
set_location_assignment PIN_E36 -to start

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name FAMILY "Stratix II GX"
set_global_assignment -name TOP_LEVEL_ENTITY thermal_top
set_global_assignment -name USER_LIBRARIES "E:/data/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/thermal_top_for_PCIe_restored/megafunctions/;E:/data/SIIGX_PCIe_Kit/Examples/ManufacturingTestDesigns/thermal_top_for_PCIe_restored/downloads/s2gx_sdi_restored/;C:/Documents and Settings/aoishei/Desktop/thermal_top_04-14-06_restored/megafunctions/;C:/Documents and Settings/aoishei/Desktop/thermal_top_04-14-06_restored/downloads/s2gx_sdi_restored/;C:/Documents and Settings/aoishei/Desktop/thermal_top_04-14-06_restored/db/;c:\\cvs_sandbox\\refdes\\sopc_builder_components/;c:\\altera\\megacore\\ddr_sdram-v2.1.1\\lib/;R:/boards/stratix2/stratix2_configuration/pld/temp_sense_working/thermal_top_working_restored/altera/quartus41/libraries/megafunctions/"
set_global_assignment -name AUTO_ENABLE_SMART_COMPILE on

# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP2SGX90FF1508C3
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 2

# Assembler Assignments
# =====================
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"

# SignalTap II Assignments
# ========================
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp

# ---------------------------------------------------
# start AUTO_INSERT_SLD_NODE_ENTITY(auto_signaltap_0)

	# SignalTap II Assignments
	# ========================

# end AUTO_INSERT_SLD_NODE_ENTITY(auto_signaltap_0)
# -------------------------------------------------

# -------------------------
# start ENTITY(thermal_top)

	# Analysis & Synthesis Assignments
	# ================================
	set_instance_assignment -name AUTO_OPEN_DRAIN_PINS ON -to smb_data

# end ENTITY(thermal_top)
# -----------------------

set_location_assignment PIN_A20 -to clk
set_instance_assignment -name IO_STANDARD LVDS -to clk
set_global_assignment -name VERILOG_FILE downloads/s2gx_sdi_restored/bus_mux2.v
set_global_assignment -name VERILOG_FILE led7seg_driver.v
set_global_assignment -name VERILOG_FILE lpm_counter_10bit.v
set_global_assignment -name VERILOG_FILE thermal.v
set_global_assignment -name VERILOG_FILE divide_by_10.v
set_global_assignment -name VERILOG_FILE thermal_top.v