user_io_bridge_tx.v

基于SIIGX的PCIe的Kit

module	user_io_bridge_tx			(
										resetn,
										clk_in,
										led_in,
										seven_seg_in,
										bridge_clk,
										bridge_data,
										bridge_cmd,
										bridge_tx_done				// Synchronous to clk
									);
// Passed parameters:
	parameter						cmd_length			=	8;		// Serial bit length
	parameter						prescale			=	2;		// >= 1       
	parameter						cmd_ssd_led			=	8'ha5;	// send led then seven seg data (24 bits)
	parameter						led_length			=	8;
	parameter						ssd_length			=	16;	

	// seven seg display
	parameter						state_ctr_width		=	4;		// ~log2(max(cmd_length,led_length_ssd_length)		
	parameter						prescale_ctr_width	=	8;		// ~log2(prescale)
	
	input							resetn;
	input							clk_in;
	input	[led_length-1:0]		led_in;
	input	[ssd_length-1:0]		seven_seg_in;
	output							bridge_clk;
	output							bridge_data;
	output							bridge_cmd;    
	output							bridge_tx_done;
	                				    
	wire							resetn;
	wire							clk_in;
	wire	[led_length-1:0]		led_in;
	wire	[ssd_length-1:0]		seven_seg_in;
	reg								bridge_clk;
	reg								bridge_data;
	reg								bridge_cmd;      
	reg								bridge_tx_done;
	
	// Internal data structures
	reg		[led_length-1:0]		led_in_reg;
	reg		[ssd_length-1:0]		seven_seg_in_reg;
	reg	[prescale_ctr_width-1:0]	prescale_ctr;

	// States
	parameter						state_cmd		=	0;
	parameter						state_led_data	=	1;
	parameter						state_ssd_data	=	2;
	parameter						state_width		=	2;			// Make enough bits to cover all states
	reg	[state_width-1:0]			state;
	reg	[state_ctr_width-1:0]		state_ctr;
	
	// Prescaler
	always	@(posedge clk_in or negedge resetn)
	begin
		if	(!resetn)
		begin
			bridge_clk			<=	0;
			bridge_data			<=	0;
			bridge_cmd			<=	0;
			prescale_ctr		<=	prescale-1;
			state				<=	state_cmd;
			state_ctr			<=	cmd_length-1;   
			bridge_tx_done		<=	0;
		end else begin
			if (prescale_ctr==0)
			begin
				prescale_ctr	<=	prescale-1;
				bridge_clk		<=	~bridge_clk;
				if	(bridge_clk)	// 0 to 1 edge
				begin
					bridge_tx_serdat;
				end
			end else begin
				prescale_ctr	<=	prescale_ctr - 1;
			end  
			if	(bridge_tx_done)
			begin
				bridge_tx_done	<=	0;	
			end
		end
	end
	                                                                                             
	// TX 3 wire interface

	task	bridge_tx_serdat;
		begin      
			case	(state)
				state_cmd:		begin
									bridge_cmd	<=	1;
									bridge_data	<=	cmd_ssd_led[state_ctr];
									if	(state_ctr != 0)
									begin
										state_ctr			<=	state_ctr - 1;	
									end else begin			// new state
										led_in_reg			<=	led_in;
										state				<=	state_led_data;
										state_ctr			<=	led_length-1;
									end             
								end                                                    
				state_led_data:	begin                     
									bridge_cmd	<=	0;
									bridge_data	<=	led_in_reg[state_ctr];
									if	(state_ctr != 0)
									begin
										state_ctr			<=	state_ctr - 1;	
									end else begin			// new state
										seven_seg_in_reg	<=	seven_seg_in;
										state				<=	state_ssd_data;
										state_ctr			<=	ssd_length-1;
									end
								end
				state_ssd_data:	begin
									bridge_cmd				<=	0;
									bridge_data				<=	seven_seg_in_reg[state_ctr];
									if	(state_ctr != 0)
									begin
										state_ctr			<=	state_ctr - 1;	
									end else begin			// new state
										state				<=	state_cmd;
										state_ctr			<=	cmd_length-1; 
										bridge_tx_done		<=	1;
									end	
								end
			endcase
		end
	endtask
endmodule