thermal_top.v

基于SIIGX的PCIe的Kit

// Copyright (C) 1991-2006 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

module thermal_top(
	clk,
	start,
	smb_clk,
	dig_a,
	dig_b,
	dig_c,
	dig_d,
	dig_e,
	dig_f,
	dig_g,
	dig_dp,
	msb_sel,
	lsb_sel,
	smb_data
);

input	clk;
input	start;
output	smb_clk;
output	dig_a;
output	dig_b;
output	dig_c;
output	dig_d;
output	dig_e;
output	dig_f;
output	dig_g;
output	dig_dp;
output	msb_sel;
output	lsb_sel;
inout	smb_data;

wire	[10:0] clock;
wire	[7:0] data;
wire	[7:0] data_;
wire	[7:0] data_lsb_;
wire	[7:0] data_msb_;
wire	[7:0] quot;
wire	[7:0] remain;
wire	[0:7] SYNTHESIZED_WIRE_0;
wire	SYNTHESIZED_WIRE_6;
wire	SYNTHESIZED_WIRE_7;
wire	SYNTHESIZED_WIRE_5;

assign	SYNTHESIZED_WIRE_0 = 0;
assign	SYNTHESIZED_WIRE_6 = 1;
assign	SYNTHESIZED_WIRE_7 = 1;
assign	SYNTHESIZED_WIRE_5 = 0;




bus_mux2	b2v_inst(.sel(clock[9]),
.data0x(data_lsb_),.data1x(data_msb_),.result(data_));

divide_by_10	b2v_inst04(.clock(clock[9]),
.denom({SYNTHESIZED_WIRE_0[0],SYNTHESIZED_WIRE_0[1],SYNTHESIZED_WIRE_0[2],SYNTHESIZED_WIRE_0[3],!SYNTHESIZED_WIRE_0[4],SYNTHESIZED_WIRE_0[5],!SYNTHESIZED_WIRE_0[6],SYNTHESIZED_WIRE_0[7]}),.numer(data),.quotient(quot),.remain(remain));

led7seg_driver	b2v_inst07(.clk(clock[9]),
.reset_n(SYNTHESIZED_WIRE_6),.dp1_n(SYNTHESIZED_WIRE_6),.count(quot[3:0]),.dig_1_a(data_msb_[7]),.dig_1_b(data_msb_[6]),.dig_1_c(data_msb_[5]),.dig_1_d(data_msb_[4]),.dig_1_e(data_msb_[3]),.dig_1_f(data_msb_[2]),.dig_1_g(data_msb_[1]),.dig_1_dp(data_msb_[0]));

led7seg_driver	b2v_inst08(.clk(clock[9]),
.reset_n(SYNTHESIZED_WIRE_7),.dp1_n(SYNTHESIZED_WIRE_7),.count(remain[3:0]),.dig_1_a(data_lsb_[7]),.dig_1_b(data_lsb_[6]),.dig_1_c(data_lsb_[5]),.dig_1_d(data_lsb_[4]),.dig_1_e(data_lsb_[3]),.dig_1_f(data_lsb_[2]),.dig_1_g(data_lsb_[1]),.dig_1_dp(data_lsb_[0]));

lpm_counter_10bit	b2v_inst09(.clock(clk),
.q(clock));
assign	msb_sel =  ~clock[9];

thermal	b2v_inst3(.clock_in(clock[9]),
.reset(SYNTHESIZED_WIRE_5),.start(start),.smb_data(smb_data),.smb_clock(smb_clk),.data_out(data));
defparam	b2v_inst3.address = 7'b0011000;
defparam	b2v_inst3.state_eight = 4'b1000;
defparam	b2v_inst3.state_eleven = 4'b1011;
defparam	b2v_inst3.state_five = 4'b0101;
defparam	b2v_inst3.state_four = 4'b0100;
defparam	b2v_inst3.state_nine = 4'b1001;
defparam	b2v_inst3.state_one = 4'b0001;
defparam	b2v_inst3.state_seven = 4'b0111;
defparam	b2v_inst3.state_six = 4'b0110;
defparam	b2v_inst3.state_ten = 4'b1010;
defparam	b2v_inst3.state_three = 4'b0011;
defparam	b2v_inst3.state_twelve = 4'b1100;
defparam	b2v_inst3.state_two = 4'b0010;
defparam	b2v_inst3.state_zero = 4'b0000;
defparam	b2v_inst3.thermal_reg = 8'b00000001;
assign	dig_a = data_[7];
assign	dig_b = data_[6];
assign	dig_c = data_[5];
assign	dig_d = data_[4];
assign	dig_e = data_[3];
assign	dig_f = data_[2];
assign	dig_g = data_[1];
assign	dig_dp = data_[0];
assign	lsb_sel = clock[9];


endmodule