cy7c1363.ftm

来自「VHDL的ram和fifo model code 包含众多的厂家」· FTM 代码 · 共 398 行 · 第 1/2 页

    (HOLD A0 CLK (0.5))
    (HOLD DQA0 CLK (0.5))
    (HOLD ADSCNeg CLK (0.5))
    (HOLD BWANeg CLK (0.5))
    (HOLD ADVNeg CLK (0.5))
    (HOLD CE2 CLK (0.5))
  )
</TIMING></FMFTIME>
<FMFTIME>
cy7c1363a-100ajc_3V3<SOURCE>Cypress 38-05259 Rev. *C Revised Jan. 18,2003</SOURCE>
cy7c1363a-100ac_3V3<SOURCE>Cypress  38-05259 Rev. *C Revised Jan. 18,2003</SOURCE>
cy7c1363a-100bgc_3V3<SOURCE>Cypress 38-05259 Rev. *C Revised Jan. 18,2003</SOURCE>
cy7c1363a-100aji_3V3<SOURCE>Cypress 38-05259 Rev. *C Revised Jan. 18,2003</SOURCE>
cy7c1363a-100ai_3V3<SOURCE>Cypress  38-05259 Rev. *C Revised Jan. 18,2003</SOURCE>
cy7c1363a-100bgi_3V3<SOURCE>Cypress 38-05259 Rev. *C Revised Jan. 18,2003</SOURCE>
<COMMENT>The values listed are for Vdd=3.135V to 3.63V, Vddq=3.3V, Ta=-40 to +85 Celsius</COMMENT>
<COMMENT>Typical values are measured at Vdd=3.3V, Vddq=3.3V, and 20 ns cycle time</COMMENT>
<TIMING>
  (DELAY (ABSOLUTE
    (IOPATH CLK DQA0 (2.7:5.4:8) (2.7:5.4:8) (2:2.8:3.5) (2.7:5.4:8) (2:2.8:3.5) (2.7:5.4:8))
    (IOPATH CLK DQA1 (2:2:2) (2:2:2) (2:2:2) (2:2:2) (2:2:2) (2:2:2))
    (IOPATH OENeg DQA0 ()()(1.2:2.4:3.5) (1.3:2.6:4)(1.2:2.4:3.5)(1.3:2.6:4))
    (IOPATH OENeg DQA1 (0:0:0) (0:0:0) (0:0:0) (0:0:0) (0:0:0) (0:0:0))
  ))
  (TIMINGCHECK
    (PERIOD (posedge CLK) (10))
    (WIDTH (posedge CLK)(3.5))
    (WIDTH (negedge CLK)(3.5))
    (SETUP A0 CLK (2))
    (SETUP DQA0 CLK (2))
    (SETUP ADVNeg CLK (2))
    (SETUP ADSCNeg CLK (2))
    (SETUP BWANeg CLK (2))
    (SETUP CE2 CLK (2))
    (HOLD A0 CLK (0.5))
    (HOLD DQA0 CLK (0.5))
    (HOLD ADSCNeg CLK (0.5))
    (HOLD BWANeg CLK (0.5))
    (HOLD ADVNeg CLK (0.5))
    (HOLD CE2 CLK (0.5))
  )
</TIMING></FMFTIME>
<FMFTIME>
cy7c1363a-100ajc_2V5<SOURCE>Cypress 38-05259 Rev. *C Revised Jan. 18,2003</SOURCE>
cy7c1363a-100ac_2V5<SOURCE>Cypress  38-05259 Rev. *C Revised Jan. 18,2003</SOURCE>
cy7c1363a-100bgc_2V5<SOURCE>Cypress 38-05259 Rev. *C Revised Jan. 18,2003</SOURCE>
cy7c1363a-100aji_2V5<SOURCE>Cypress 38-05259 Rev. *C Revised Jan. 18,2003</SOURCE>
cy7c1363a-100ai_2V5<SOURCE>Cypress  38-05259 Rev. *C Revised Jan. 18,2003</SOURCE>
cy7c1363a-100bgi_2V5<SOURCE>Cypress 38-05259 Rev. *C Revised Jan. 18,2003</SOURCE>
<COMMENT>The values listed are for Vdd=3.135V to 3.63V, Vddq=2.5V, Ta=-40 to +85 Celsius</COMMENT>
<COMMENT>Typical values are measured at Vdd=3.3V, Vddq=2.5V, and 20 ns cycle time</COMMENT>
<TIMING>
  (DELAY (ABSOLUTE
    (IOPATH CLK DQA0 (3:6:9) (3:6:9) (2:2.8:3.5) (3:6:9) (2:2.8:3.5) (3:6:9))
    (IOPATH CLK DQA1 (2:2:2) (2:2:2) (2:2:2) (2:2:2) (2:2:2) (2:2:2))
    (IOPATH OENeg DQA0 ()()(1.2:2.4:3.5) (1.7:3.4:5)(1.2:2.4:3.5)(1.7:3.4:5))
    (IOPATH OENeg DQA1 (0:0:0) (0:0:0) (0:0:0) (0:0:0) (0:0:0) (0:0:0))
  ))
  (TIMINGCHECK
    (PERIOD (posedge CLK) (10))
    (WIDTH (posedge CLK)(3.5))
    (WIDTH (negedge CLK)(3.5))
    (SETUP A0 CLK (2))
    (SETUP DQA0 CLK (2))
    (SETUP ADVNeg CLK (2))
    (SETUP ADSCNeg CLK (2))
    (SETUP BWANeg CLK (2))
    (SETUP CE2 CLK (2))
    (HOLD A0 CLK (0.5))
    (HOLD DQA0 CLK (0.5))
    (HOLD ADSCNeg CLK (0.5))
    (HOLD BWANeg CLK (0.5))
    (HOLD ADVNeg CLK (0.5))
    (HOLD CE2 CLK (0.5))
  )
</TIMING></FMFTIME>
<FMFTIME>
gs881f18at-7<SOURCE>Giga Semiconductor, Inc. Datasheet 512K x 18 Sync Burst SRAM Rev. 1.00 June,2003</SOURCE>
<COMMENT>The values listed are for Vdd=3V to 3.6V, Ta=-40 to +85 Celsius</COMMENT>
<TIMING>
  (DELAY (ABSOLUTE
    (IOPATH CLK DQA0 (3:4.8:7) (3:4.8:7) (1.5:2.3:3) (3:4.8:7) (1.5:2.3:3) (3:4.8:7))
    (IOPATH CLK DQA1 (3:3:3) (3:3:3) (3:3:3) (3:3:3) (3:3:3) (3:3:3))
    (IOPATH OENeg DQA0 ()()(1:2:3) (1.2:2.4:3.5)(1:2:3)(1.2:2.4:3.5))
    (IOPATH OENeg DQA1 (0:0:0) (0:0:0) (0:0:0) (0:0:0) (0:0:0) (0:0:0))
  ))
  (TIMINGCHECK
    (PERIOD (posedge CLK) (7))
    (WIDTH (posedge CLK)(1.3))
    (WIDTH (negedge CLK)(1.5))
    (SETUP A0 CLK (1.5))
    (SETUP DQA0 CLK (1.5))
    (SETUP ADVNeg CLK (1.5))
    (SETUP ADSCNeg CLK (1.5))
    (SETUP BWANeg CLK (1.5))
    (SETUP CE2 CLK (1.5))
    (HOLD A0 CLK (0.5))
    (HOLD DQA0 CLK (0.5))
    (HOLD ADSCNeg CLK (0.5))
    (HOLD BWANeg CLK (0.5))
    (HOLD ADVNeg CLK (0.5))
    (HOLD CE2 CLK (0.5))
  )
</TIMING></FMFTIME>
<FMFTIME>
cy7c1363b-133ajc<SOURCE>Cypress 38-05302 Rev. ** Revised Aug. 16,2002</SOURCE>
cy7c1363b-133ac<SOURCE>Cypress  38-05302 Rev. ** Revised Aug. 16,2002</SOURCE>
cy7c1363b-133bgc<SOURCE>Cypress 38-05302 Rev. ** Revised Aug. 16,2002</SOURCE>
cy7c1363b-133bzc<SOURCE>Cypress 38-05302 Rev. ** Revised Aug. 16,2002</SOURCE>
<COMMENT>The values listed are for Vdd=3.135V to 3.6V, Ta=0 to +70 Celsius</COMMENT>
<TIMING>
  (DELAY (ABSOLUTE
    (IOPATH CLK DQA0 (2.2:4.4:6.5) (2.2:4.4:6.5) (0:1.8:3.5) (2.2:4.4:6.5) (0:1.8:3.5) (2.2:4.4:6.5))
    (IOPATH CLK DQA1 (2:2:2) (2:2:2) (2:2:2) (2:2:2) (2:2:2) (2:2:2))
    (IOPATH OENeg DQA0 ()()(1.2:2.4:3.5) (1.2:2.4:3.5)(1.2:2.4:3.5)(1.2:2.4:3.5))
    (IOPATH OENeg DQA1 (0:0:0) (0:0:0) (0:0:0) (0:0:0) (0:0:0) (0:0:0))
  ))
  (TIMINGCHECK
    (PERIOD (posedge CLK) (7.5))
    (WIDTH (posedge CLK)(3))
    (WIDTH (negedge CLK)(3))
    (SETUP A0 CLK (1.5))
    (SETUP DQA0 CLK (1.5))
    (SETUP ADVNeg CLK (1.5))
    (SETUP ADSCNeg CLK (1.5))
    (SETUP BWANeg CLK (1.5))
    (SETUP CE2 CLK (1.5))
    (HOLD A0 CLK (0.5))
    (HOLD DQA0 CLK (0.5))
    (HOLD ADSCNeg CLK (0.5))
    (HOLD BWANeg CLK (0.5))
    (HOLD ADVNeg CLK (0.5))
    (HOLD CE2 CLK (0.5))
  )
</TIMING></FMFTIME>
<FMFTIME>
cy7c1363b-117ajc<SOURCE>Cypress 38-05302 Rev. ** Revised Aug. 16,2002</SOURCE>
cy7c1363b-117ac<SOURCE>Cypress  38-05302 Rev. ** Revised Aug. 16,2002</SOURCE>
cy7c1363b-117bgc<SOURCE>Cypress 38-05302 Rev. ** Revised Aug. 16,2002</SOURCE>
cy7c1363b-117bzc<SOURCE>Cypress 38-05302 Rev. ** Revised Aug. 16,2002</SOURCE>
<COMMENT>The values listed are for Vdd=3.135V to 3.6V, Ta=0 to +70 Celsius</COMMENT>
<TIMING>
  (DELAY (ABSOLUTE
    (IOPATH CLK DQA0 (2.5:5:7.5) (2.5:5:7.5) (0:1.8:3.5) (2.5:5:7.5) (0:1.8:3.5) (2.5:5:7.5))
    (IOPATH CLK DQA1 (2:2:2) (2:2:2) (2:2:2) (2:2:2) (2:2:2) (2:2:2))
    (IOPATH OENeg DQA0 ()()(1.2:2.4:3.5) (1.2:2.4:3.5)(1.2:2.4:3.5)(1.2:2.4:3.5))
    (IOPATH OENeg DQA1 (0:0:0) (0:0:0) (0:0:0) (0:0:0) (0:0:0) (0:0:0))
  ))
  (TIMINGCHECK
    (PERIOD (posedge CLK) (8.5))
    (WIDTH (posedge CLK)(3.2))
    (WIDTH (negedge CLK)(3.2))
    (SETUP A0 CLK (1.5))
    (SETUP DQA0 CLK (1.5))
    (SETUP ADVNeg CLK (1.5))
    (SETUP ADSCNeg CLK (1.5))
    (SETUP BWANeg CLK (1.5))
    (SETUP CE2 CLK (1.5))
    (HOLD A0 CLK (0.5))
    (HOLD DQA0 CLK (0.5))
    (HOLD ADSCNeg CLK (0.5))
    (HOLD BWANeg CLK (0.5))
    (HOLD ADVNeg CLK (0.5))
    (HOLD CE2 CLK (0.5))
  )
</TIMING></FMFTIME>
<FMFTIME>
cy7c1363b-100ajc<SOURCE>Cypress 38-05302 Rev. ** Revised Aug. 16,2002</SOURCE>
cy7c1363b-100ac<SOURCE>Cypress  38-05302 Rev. ** Revised Aug. 16,2002</SOURCE>
cy7c1363b-100bgc<SOURCE>Cypress 38-05302 Rev. ** Revised Aug. 16,2002</SOURCE>
cy7c1363b-100bzc<SOURCE>Cypress 38-05302 Rev. ** Revised Aug. 16,2002</SOURCE>
<COMMENT>The values listed are for Vdd=3.135V to 3.6V, Ta=0 to +70 Celsius</COMMENT>
<TIMING>
  (DELAY (ABSOLUTE
    (IOPATH CLK DQA0 (2.8:5.6:8.5) (2.8:5.6:8.5) (0:1.8:3.5) (2.8:5.6:8.5) (0:1.8:3.5) (2.8:5.6:8.5))
    (IOPATH CLK DQA1 (2:2:2) (2:2:2) (2:2:2) (2:2:2) (2:2:2) (2:2:2))
    (IOPATH OENeg DQA0 ()()(1.2:2.4:3.5) (1.2:2.4:3.5)(1.2:2.4:3.5)(1.2:2.4:3.5))
    (IOPATH OENeg DQA1 (0:0:0) (0:0:0) (0:0:0) (0:0:0) (0:0:0) (0:0:0))
  ))
  (TIMINGCHECK
    (PERIOD (posedge CLK) (10))
    (WIDTH (posedge CLK)(4))
    (WIDTH (negedge CLK)(4))
    (SETUP A0 CLK (1.5))
    (SETUP DQA0 CLK (1.5))
    (SETUP ADVNeg CLK (1.5))
    (SETUP ADSCNeg CLK (1.5))
    (SETUP BWANeg CLK (1.5))
    (SETUP CE2 CLK (1.5))
    (HOLD A0 CLK (0.5))
    (HOLD DQA0 CLK (0.5))
    (HOLD ADSCNeg CLK (0.5))
    (HOLD BWANeg CLK (0.5))
    (HOLD ADVNeg CLK (0.5))
    (HOLD CE2 CLK (0.5))
  )
</TIMING></FMFTIME>
</BODY></FTML>