cy7c1363.ftm

来自「VHDL的ram和fifo model code 包含众多的厂家」· FTM 代码 · 共 398 行 · 第 1/2 页
FTM
398 行
 <!DOCTYPE FTML SYSTEM "ftml.dtd"><FTML><HEAD><TITLE>FMF Timing for cy7c1363 model</TITLE><BODY><REVISION.HISTORY>version: |  author:         | mod date: | changes made:  V1.0    D.Randjelovic       05 Nov 28   Initial release</REVISION.HISTORY><TIMESCALE>1ns</TIMESCALE><MODEL>cy7c1363<FMFTIME>cy7c1363a-150ajc_3V3<SOURCE>Cypress 38-05259 Rev. *C Revised Jan. 18,2003</SOURCE>cy7c1363a-150ac_3V3<SOURCE>Cypress  38-05259 Rev. *C Revised Jan. 18,2003</SOURCE>cy7c1363a-150bgc_3V3<SOURCE>Cypress 38-05259 Rev. *C Revised Jan. 18,2003</SOURCE><COMMENT>The values listed are for Vdd=3.135V to 3.63V, Vddq=3.3V, Ta=0 to +70 Celsius</COMMENT><COMMENT>Typical values are measured at Vdd=3.3V, Vddq=3.3V, and 20 ns cycle time</COMMENT><TIMING>  (DELAY (ABSOLUTE    (IOPATH CLK DQA0 (2:4:6) (2:4:6) (2:2.8:3.5) (2:4:6) (2:2.8:3.5) (2:4:6))    (IOPATH CLK DQA1 (2:2:2) (2:2:2) (2:2:2) (2:2:2) (2:2:2) (2:2:2))    (IOPATH OENeg DQA0 ()()(1.2:2.4:3.5) (1.2:2.4:3.5)(1.2:2.4:3.5)(1.2:2.4:3.5))    (IOPATH OENeg DQA1 (0:0:0) (0:0:0) (0:0:0) (0:0:0) (0:0:0) (0:0:0))  ))  (TIMINGCHECK    (PERIOD (posedge CLK) (6.7))    (WIDTH (posedge CLK)(2.5))    (WIDTH (negedge CLK)(2.5))    (SETUP A0 CLK (1.5))    (SETUP DQA0 CLK (1.5))    (SETUP ADVNeg CLK (1.5))    (SETUP ADSCNeg CLK (1.5))    (SETUP BWANeg CLK (1.5))    (SETUP CE2 CLK (1.5))    (HOLD A0 CLK (0.5))    (HOLD DQA0 CLK (0.5))    (HOLD ADSCNeg CLK (0.5))    (HOLD BWANeg CLK (0.5))    (HOLD ADVNeg CLK (0.5))    (HOLD CE2 CLK (0.5))  )</TIMING></FMFTIME><FMFTIME>cy7c1363a-150ajc_2V5<SOURCE>Cypress 38-05259 Rev. *C Revised Jan. 18,2003</SOURCE>cy7c1363a-150ac_2V5<SOURCE>Cypress  38-05259 Rev. *C Revised Jan. 18,2003</SOURCE>cy7c1363a-150bgc_2V5<SOURCE>Cypress 38-05259 Rev. *C Revised Jan. 18,2003</SOURCE><COMMENT>The values listed are for Vdd=3.135V to 3.63V, Vddq=2.5V, Ta=0 to +70 Celsius</COMMENT><COMMENT>Typical values are measured at Vdd=3.3V, Vddq=2.5V, and 20 ns cycle time</COMMENT><TIMING>  (DELAY (ABSOLUTE    (IOPATH CLK DQA0 (2.2:4.4:6.5) (2.2:4.4:6.5) (2:2.8:3.5) (2.2:4.4:6.5) (2:2.8:3.5) (2.2:4.4:6.5))    (IOPATH CLK DQA1 (2:2:2) (2:2:2) (2:2:2) (2:2:2) (2:2:2) (2:2:2))    (IOPATH OENeg DQA0 ()()(1.2:2.4:3.5) (1.5:3:4.5)(1.2:2.4:3.5)(1.5:3:4.5))    (IOPATH OENeg DQA1 (0:0:0) (0:0:0) (0:0:0) (0:0:0) (0:0:0) (0:0:0))  ))  (TIMINGCHECK    (PERIOD (posedge CLK) (6.7))    (WIDTH (posedge CLK)(2.5))    (WIDTH (negedge CLK)(2.5))    (SETUP A0 CLK (1.5))    (SETUP DQA0 CLK (1.5))    (SETUP ADVNeg CLK (1.5))    (SETUP ADSCNeg CLK (1.5))    (SETUP BWANeg CLK (1.5))    (SETUP CE2 CLK (1.5))    (HOLD A0 CLK (0.5))    (HOLD DQA0 CLK (0.5))    (HOLD ADSCNeg CLK (0.5))    (HOLD BWANeg CLK (0.5))    (HOLD ADVNeg CLK (0.5))    (HOLD CE2 CLK (0.5))  )</TIMING></FMFTIME><FMFTIME>cy7c1363a-133ajc_3V3<SOURCE>Cypress 38-05259 Rev. *C Revised Jan. 18,2003</SOURCE>cy7c1363a-133ac_3V3<SOURCE>Cypress  38-05259 Rev. *C Revised Jan. 18,2003</SOURCE>cy7c1363a-133bgc_3V3<SOURCE>Cypress 38-05259 Rev. *C Revised Jan. 18,2003</SOURCE>cy7c1363a-133aji_3V3<SOURCE>Cypress 38-05259 Rev. *C Revised Jan. 18,2003</SOURCE>cy7c1363a-133ai_3V3<SOURCE>Cypress  38-05259 Rev. *C Revised Jan. 18,2003</SOURCE>cy7c1363a-133bgi_3V3<SOURCE>Cypress 38-05259 Rev. *C Revised Jan. 18,2003</SOURCE><COMMENT>The values listed are for Vdd=3.135V to 3.63V, Vddq=3.3V, Ta=-40 to +85 Celsius</COMMENT><COMMENT>Typical values are measured at Vdd=3.3V, Vddq=3.3V, and 20 ns cycle time</COMMENT><TIMING>  (DELAY (ABSOLUTE    (IOPATH CLK DQA0 (2.2:4.4:6.5) (2.2:4.4:6.5) (2:2.8:3.5) (2.2:4.4:6.5) (2:2.8:3.5) (2.2:4.4:6.5))    (IOPATH CLK DQA1 (2:2:2) (2:2:2) (2:2:2) (2:2:2) (2:2:2) (2:2:2))    (IOPATH OENeg DQA0 ()()(1.2:2.4:3.5) (1.2:2.4:3.5)(1.2:2.4:3.5)(1.2:2.4:3.5))    (IOPATH OENeg DQA1 (0:0:0) (0:0:0) (0:0:0) (0:0:0) (0:0:0) (0:0:0))  ))  (TIMINGCHECK    (PERIOD (posedge CLK) (7.5))    (WIDTH (posedge CLK)(2.5))    (WIDTH (negedge CLK)(2.5))    (SETUP A0 CLK (1.5))    (SETUP DQA0 CLK (1.5))    (SETUP ADVNeg CLK (1.5))    (SETUP ADSCNeg CLK (1.5))    (SETUP BWANeg CLK (1.5))    (SETUP CE2 CLK (1.5))    (HOLD A0 CLK (0.5))    (HOLD DQA0 CLK (0.5))    (HOLD ADSCNeg CLK (0.5))    (HOLD BWANeg CLK (0.5))    (HOLD ADVNeg CLK (0.5))    (HOLD CE2 CLK (0.5))  )</TIMING></FMFTIME><FMFTIME>cy7c1363a-133ajc_2V5<SOURCE>Cypress 38-05259 Rev. *C Revised Jan. 18,2003</SOURCE>cy7c1363a-133ac_2V5<SOURCE>Cypress  38-05259 Rev. *C Revised Jan. 18,2003</SOURCE>cy7c1363a-133bgc_2V5<SOURCE>Cypress 38-05259 Rev. *C Revised Jan. 18,2003</SOURCE>cy7c1363a-133aji_2V5<SOURCE>Cypress 38-05259 Rev. *C Revised Jan. 18,2003</SOURCE>cy7c1363a-133ai_2V5<SOURCE>Cypress  38-05259 Rev. *C Revised Jan. 18,2003</SOURCE>cy7c1363a-133bgi_2V5<SOURCE>Cypress 38-05259 Rev. *C Revised Jan. 18,2003</SOURCE><COMMENT>The values listed are for Vdd=3.135V to 3.63V, Vddq=2.5V, Ta=-40 to +85 Celsius</COMMENT><COMMENT>Typical values are measured at Vdd=3.3V, Vddq=2.5V, and 20 ns cycle time</COMMENT><TIMING>  (DELAY (ABSOLUTE    (IOPATH CLK DQA0 (2.4:4.8:7) (2.4:4.8:7) (2:2.8:3.5) (2.4:4.8:7) (2:2.8:3.5) (2.4:4.8:7))    (IOPATH CLK DQA1 (2:2:2) (2:2:2) (2:2:2) (2:2:2) (2:2:2) (2:2:2))    (IOPATH OENeg DQA0 ()()(1.2:2.4:3.5) (1.5:3:4.5)(1.2:2.4:3.5)(1.5:3:4.5))    (IOPATH OENeg DQA1 (0:0:0) (0:0:0) (0:0:0) (0:0:0) (0:0:0) (0:0:0))  ))  (TIMINGCHECK    (PERIOD (posedge CLK) (7.5))    (WIDTH (posedge CLK)(2.5))    (WIDTH (negedge CLK)(2.5))    (SETUP A0 CLK (1.5))    (SETUP DQA0 CLK (1.5))    (SETUP ADVNeg CLK (1.5))    (SETUP ADSCNeg CLK (1.5))    (SETUP BWANeg CLK (1.5))    (SETUP CE2 CLK (1.5))    (HOLD A0 CLK (0.5))    (HOLD DQA0 CLK (0.5))    (HOLD ADSCNeg CLK (0.5))    (HOLD BWANeg CLK (0.5))    (HOLD ADVNeg CLK (0.5))    (HOLD CE2 CLK (0.5))  )</TIMING></FMFTIME><FMFTIME>cy7c1363a-117ajc_3V3<SOURCE>Cypress 38-05259 Rev. *C Revised Jan. 18,2003</SOURCE>cy7c1363a-117ac_3V3<SOURCE>Cypress  38-05259 Rev. *C Revised Jan. 18,2003</SOURCE>cy7c1363a-117bgc_3V3<SOURCE>Cypress 38-05259 Rev. *C Revised Jan. 18,2003</SOURCE>cy7c1363a-117aji_3V3<SOURCE>Cypress 38-05259 Rev. *C Revised Jan. 18,2003</SOURCE>cy7c1363a-117ai_3V3<SOURCE>Cypress  38-05259 Rev. *C Revised Jan. 18,2003</SOURCE>cy7c1363a-117bgi_3V3<SOURCE>Cypress 38-05259 Rev. *C Revised Jan. 18,2003</SOURCE><COMMENT>The values listed are for Vdd=3.135V to 3.63V, Vddq=3.3V, Ta=-40 to +85 Celsius</COMMENT><COMMENT>Typical values are measured at Vdd=3.3V, Vddq=3.3V, and 20 ns cycle time</COMMENT><TIMING>  (DELAY (ABSOLUTE    (IOPATH CLK DQA0 (2.4:4.8:7) (2.4:4.8:7) (2:2.8:3.5) (2.4:4.8:7) (2:2.8:3.5) (2.4:4.8:7))    (IOPATH CLK DQA1 (2:2:2) (2:2:2) (2:2:2) (2:2:2) (2:2:2) (2:2:2))    (IOPATH OENeg DQA0 ()()(1.2:2.4:3.5) (1.2:2.4:3.5)(1.2:2.4:3.5)(1.2:2.4:3.5))    (IOPATH OENeg DQA1 (0:0:0) (0:0:0) (0:0:0) (0:0:0) (0:0:0) (0:0:0))  ))  (TIMINGCHECK    (PERIOD (posedge CLK) (8.5))    (WIDTH (posedge CLK)(3))    (WIDTH (negedge CLK)(3))    (SETUP A0 CLK (1.8))    (SETUP DQA0 CLK (1.8))    (SETUP ADVNeg CLK (1.8))    (SETUP ADSCNeg CLK (1.8))    (SETUP BWANeg CLK (1.8))    (SETUP CE2 CLK (1.8))    (HOLD A0 CLK (0.5))    (HOLD DQA0 CLK (0.5))    (HOLD ADSCNeg CLK (0.5))    (HOLD BWANeg CLK (0.5))    (HOLD ADVNeg CLK (0.5))    (HOLD CE2 CLK (0.5))  )</TIMING></FMFTIME><FMFTIME>cy7c1363a-117ajc_2V5<SOURCE>Cypress 38-05259 Rev. *C Revised Jan. 18,2003</SOURCE>cy7c1363a-117ac_2V5<SOURCE>Cypress  38-05259 Rev. *C Revised Jan. 18,2003</SOURCE>cy7c1363a-117bgc_2V5<SOURCE>Cypress 38-05259 Rev. *C Revised Jan. 18,2003</SOURCE>cy7c1363a-117aji_2V5<SOURCE>Cypress 38-05259 Rev. *C Revised Jan. 18,2003</SOURCE>cy7c1363a-117ai_2V5<SOURCE>Cypress  38-05259 Rev. *C Revised Jan. 18,2003</SOURCE>cy7c1363a-117bgi_2V5<SOURCE>Cypress 38-05259 Rev. *C Revised Jan. 18,2003</SOURCE><COMMENT>The values listed are for Vdd=3.135V to 3.63V, Vddq=2.5V, Ta=-40 to +85 Celsius</COMMENT><COMMENT>Typical values are measured at Vdd=3.3V, Vddq=2.5V, and 20 ns cycle time</COMMENT><TIMING>  (DELAY (ABSOLUTE    (IOPATH CLK DQA0 (2.5:5:7.5) (2.5:5:7.5) (2:2.8:3.5) (2.5:5:7.5) (2:2.8:3.5) (2.5:5:7.5))    (IOPATH CLK DQA1 (2:2:2) (2:2:2) (2:2:2) (2:2:2) (2:2:2) (2:2:2))    (IOPATH OENeg DQA0 ()()(1.2:2.4:3.5) (1.5:3:4.5)(1.2:2.4:3.5)(1.5:3:4.5))    (IOPATH OENeg DQA1 (0:0:0) (0:0:0) (0:0:0) (0:0:0) (0:0:0) (0:0:0))  ))  (TIMINGCHECK    (PERIOD (posedge CLK) (8.5))    (WIDTH (posedge CLK)(3))    (WIDTH (negedge CLK)(3))    (SETUP A0 CLK (1.8))    (SETUP DQA0 CLK (1.8))    (SETUP ADVNeg CLK (1.8))    (SETUP ADSCNeg CLK (1.8))    (SETUP BWANeg CLK (1.8))    (SETUP CE2 CLK (1.8))
cy7c1363.ftm - 源码说明

本页面展示了「VHDL的ram和fifo model code 包含众多的厂家」中的 cy7c1363.ftm 源码文件，采用 FTM 编程语言编写，共 398 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。
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