idt70v5388.ftm
来自「VHDL的ram和fifo model code 包含众多的厂家」· FTM 代码 · 共 227 行
FTM
227 行
<!DOCTYPE FTML SYSTEM "ftml.dtd"><FTML><HEAD><TITLE>FMF Timing for idt70v5388 Parts</TITLE><BODY><REVISION.HISTORY>version: | author: | mod date: | changes made: V1.0 R. Munden 03 Sep 25 Initial release</REVISION.HISTORY><TIMESCALE>1ns</TIMESCALE><MODEL>idt70v5388<FMFTIME>IDT70V5388S200BC<SOURCE>Integrated Device Technology DSC 5649/3 August 2003</SOURCE>IDT70V5388S200BG<SOURCE>Integrated Device Technology DSC 5649/3 August 2003</SOURCE><COMMENT>The Values listed are for VCC=3.3V +/- 150mV, CL=10pF, Ta=0 to 70C</COMMENT><COMMENT>For each parameter only minimum or maximum values were provided by the vendor, other values are derived</COMMENT><TIMING> (DELAY (ABSOLUTE (IOPATH CLK IO0 (1.0:2.0:3.0) (1.0:2.0:3.0) (1.0:2.0:3.0) (1.0:2.0:3.0) (1.0:2.0:3.0) (1.0:2.0:3.0)) (IOPATH OENeg IO0 () () (1.0:2.2:3.4) (1.0:2.0:4.0) (1.0:2.2:3.4) (1.0:2.0:4.0)) (IOPATH TCK TDO (7.0:14.0:20.0) (7.0:14.0:20.0)) (IOPATH CLK A0 (1.1:2.2:3.4) (1.1:2.2:3.4)) (IOPATH MRSTNeg INTNeg (2.2:4.4:6.5) ()) (IOPATH CLK CNTINTNeg (1.7:3.4:5.0) (1.7:3.4:5.0)) (IOPATH CLK INTNeg (1.7:3.4:5.0) (1.7:3.4:5.0)) )) (TIMINGCHECK (PERIOD (posedge CLK) (5.0)) (PERIOD (posedge TCK) (100.0)) (WIDTH (posedge CLK) (2.0)) (WIDTH (negedge CLK) (2.0)) (WIDTH (posedge TCK) (40.0)) (WIDTH (negedge TCK) (40.0)) (WIDTH (negedge MRSTNeg) (7.5)) (WIDTH (negedge TRSTNeg) (50.0)) (SETUP A0 CLK (1.5)) (SETUP IO0 CLK (1.5)) (SETUP RW CLK (1.5)) (SETUP CE1 CLK (1.5)) (SETUP LBNeg CLK (1.5)) (SETUP CNTLDNeg CLK (1.5)) (SETUP CNTINCNeg CLK (1.5)) (SETUP CNTRSTNeg CLK (1.5)) (SETUP CNTRDNeg CLK (1.5)) (SETUP MKLDNeg CLK (1.5)) (SETUP MKLDNeg CLK (1.5)) (SETUP TDI TCK (1.5)) (HOLD A0 CLK (0.5)) (HOLD IO0 CLK (0.5)) (HOLD RW CLK (0.5)) (HOLD CE1 CLK (0.5)) (HOLD LBNeg CLK (0.5)) (HOLD CNTLDNeg CLK (0.5)) (HOLD CNTINCNeg CLK (0.5)) (HOLD CNTRSTNeg CLK (0.5)) (HOLD CNTRDNeg CLK (0.5)) (HOLD MKLDNeg CLK (0.5)) (HOLD MKLDNeg CLK (0.5)) (HOLD TDI TCK (0.5)) (RECOVERY MRSTNeg CLK (7.5)) (RECOVERY TRSTNeg TCK (50.0)) )) (CELL (CELLTYPE "VITALbuf" ) (INSTANCE %LABEL%/TCCS) (DELAY (ABSOLUTE ( DEVICE (4.5) ) ) )</TIMING></FMFTIME><FMFTIME>IDT70V5388S166BC<SOURCE>Integrated Device Technology DSC 5649/3 August 2003</SOURCE>IDT70V5388S166BG<SOURCE>Integrated Device Technology DSC 5649/3 August 2003</SOURCE><COMMENT>The Values listed are for VCC=3.3V +/- 150mV, CL=10pF, Ta=0 to 70C</COMMENT><COMMENT>For each parameter only minimum or maximum values were provided by the vendor, other values are derived</COMMENT><TIMING> (DELAY (ABSOLUTE (IOPATH CLK IO0 (1.1:2.1:3.2) (1.1:2.2:3.2) (1.0:2.0:3.0) (1.1:2.2:3.2) (1.0:2.0:3.0) (1.1:2.1:3.2)) (IOPATH OENeg IO0 () () (1.0:2.4:3.6) (1.0:2.6:4.0) (1.0:2.4:3.6) (1.0:2.6:4.0)) (IOPATH TCK TDO (20.0:20.0:20.0) (20.0:20.0:20.0)) (IOPATH CLK A0 (1.2:2.4:3.6) (1.2:2.4:3.6)) (IOPATH MRSTNeg INTNeg (2.2:4.4:6.5) ()) (IOPATH CLK CNTINTNeg (2.0:4.0:6.0) (2.0:4.0:6.0)) (IOPATH CLK INTNeg (2.0:4.0:6.0) (2.0:4.0:6.0)) )) (TIMINGCHECK (PERIOD (posedge CLK) (6.0)) (PERIOD (posedge TCK) (100.0)) (WIDTH (posedge CLK) (2.1)) (WIDTH (negedge CLK) (2.1)) (WIDTH (posedge TCK) (40.0)) (WIDTH (negedge TCK) (40.0)) (WIDTH (negedge MRSTNeg) (7.5)) (WIDTH (negedge TRSTNeg) (50.0)) (SETUP A0 CLK (1.7)) (SETUP IO0 CLK (1.7)) (SETUP RW CLK (1.7)) (SETUP CE1 CLK (1.7)) (SETUP LBNeg CLK (1.7)) (SETUP CNTLDNeg CLK (1.7)) (SETUP CNTINCNeg CLK (1.7)) (SETUP CNTRSTNeg CLK (1.7)) (SETUP CNTRDNeg CLK (1.7)) (SETUP MKLDNeg CLK (1.7)) (SETUP MKLDNeg CLK (1.7)) (SETUP TDI TCK (1.7)) (HOLD A0 CLK (0.5)) (HOLD IO0 CLK (0.5)) (HOLD RW CLK (0.5)) (HOLD CE1 CLK (0.5)) (HOLD LBNeg CLK (0.5)) (HOLD CNTLDNeg CLK (0.5)) (HOLD CNTINCNeg CLK (0.5)) (HOLD CNTRSTNeg CLK (0.5)) (HOLD CNTRDNeg CLK (0.5)) (HOLD MKLDNeg CLK (0.5)) (HOLD MKLDNeg CLK (0.5)) (HOLD TDI TCK (0.5)) (RECOVERY MRSTNeg CLK (7.5)) (RECOVERY TRSTNeg TCK (50.0)) )) (CELL (CELLTYPE "VITALbuf" ) (INSTANCE %LABEL%/TCCS) (DELAY (ABSOLUTE ( DEVICE (5.0) ) ) )</TIMING></FMFTIME><FMFTIME>IDT70V5388S133BC<SOURCE>Integrated Device Technology DSC 5649/3 August 2003</SOURCE>IDT70V5388S133BG<SOURCE>Integrated Device Technology DSC 5649/3 August 2003</SOURCE><COMMENT>The Values listed are for VCC=3.3V +/- 150mV, CL=10pF, Ta=0 to 70C</COMMENT><COMMENT>For each parameter only minimum or maximum values were provided by the vendor, other values are derived</COMMENT><TIMING> (DELAY (ABSOLUTE (IOPATH CLK IO0 (1.1:2.2:3.4) (1.1:2.2:3.4) (1.0:2.0:3.0) (1.0:2.2:3.4) (1.0:2.0:3.0) (1.0:2.2:3.4)) (IOPATH OENeg IO0 () () (1.0:2.8:4.2) (1.0:2.8:4.2) (1.0:2.8:4.2) (1.0:2.8:4.2)) (IOPATH TCK TDO (20.0:20.0:20.0) (20.0:20.0:20.0)) (IOPATH CLK A0 (1.4:2.8:4.2) (1.4:2.8:4.2)) (IOPATH MRSTNeg INTNeg (2.2:4.4:6.5) ()) (IOPATH CLK CNTINTNeg (2.8:5.6:7.5) (2.8:5.6:7.5)) (IOPATH CLK INTNeg (2.8:5.6:7.5) (2.8:5.6:7.5)) )) (TIMINGCHECK (PERIOD (posedge CLK) (7.5)) (PERIOD (posedge TCK) (100.0)) (WIDTH (posedge CLK) (2.6)) (WIDTH (negedge CLK) (2.6)) (WIDTH (posedge TCK) (40.0)) (WIDTH (negedge TCK) (40.0)) (WIDTH (negedge MRSTNeg) (7.5)) (WIDTH (negedge TRSTNeg) (50.0)) (SETUP A0 CLK (1.8)) (SETUP IO0 CLK (1.8)) (SETUP RW CLK (1.8)) (SETUP CE1 CLK (1.8)) (SETUP LBNeg CLK (1.8)) (SETUP CNTLDNeg CLK (1.8)) (SETUP CNTINCNeg CLK (1.8)) (SETUP CNTRSTNeg CLK (1.8)) (SETUP CNTRDNeg CLK (1.8)) (SETUP MKLDNeg CLK (1.8)) (SETUP MKLDNeg CLK (1.8)) (SETUP TDI TCK (1.8)) (HOLD A0 CLK (0.5)) (HOLD IO0 CLK (0.5)) (HOLD RW CLK (0.5)) (HOLD CE1 CLK (0.5)) (HOLD LBNeg CLK (0.5)) (HOLD CNTLDNeg CLK (0.5)) (HOLD CNTINCNeg CLK (0.5)) (HOLD CNTRSTNeg CLK (0.5)) (HOLD CNTRDNeg CLK (0.5)) (HOLD MKLDNeg CLK (0.5)) (HOLD MKLDNeg CLK (0.5)) (HOLD TDI TCK (0.5)) (RECOVERY MRSTNeg CLK (7.5)) (RECOVERY TRSTNeg TCK (50.0)) )) (CELL (CELLTYPE "VITALbuf" ) (INSTANCE %LABEL%/TCCS) (DELAY (ABSOLUTE ( DEVICE (6.5) ) ) )</TIMING></FMFTIME><FMFTIME>IDT70V5388S100BC<SOURCE>Integrated Device Technology DSC 5649/3 August 2003</SOURCE>IDT70V5388S100BG<SOURCE>Integrated Device Technology DSC 5649/3 August 2003</SOURCE><COMMENT>The Values listed are for VCC=3.3V +/- 150mV, CL=10pF, Ta=0 to 70C</COMMENT><COMMENT>For each parameter only minimum or maximum values were provided by the vendor, other values are derived</COMMENT><TIMING> (DELAY (ABSOLUTE (IOPATH CLK IO0 (1.2:2.4:3.6) (1.2:2.4:3.6) (1.0:2.0:3.0) (1.0:2.4:3.6) (1.0:2.0:3.0) (1.0:2.4:3.6)) (IOPATH OENeg IO0 () () (1.0:3.0:4.5) (1.0:3.4:5.0) (1.0:3.0:4.5) (1.0:3.4:5.0)) (IOPATH TCK TDO (20.0:20.0:20.0) (20.0:20.0:20.0)) (IOPATH CLK A0 (1.8:3.4:5.0) (1.8:3.4:5.0)) (IOPATH MRSTNeg INTNeg (2.7:5.4:8.0) ()) (IOPATH CLK CNTINTNeg (3.3:6.7:10.0) (3.3:6.7:10.0)) (IOPATH CLK INTNeg (3.3:6.7:10.0) (3.3:6.7:10.0)) )) (TIMINGCHECK (PERIOD (posedge CLK) (10.0)) (PERIOD (posedge TCK) (100.0)) (WIDTH (posedge CLK) (4.0)) (WIDTH (negedge CLK) (4.0)) (WIDTH (posedge TCK) (40.0)) (WIDTH (negedge TCK) (40.0)) (WIDTH (negedge MRSTNeg) (10.0)) (WIDTH (negedge TRSTNeg) (50.0)) (SETUP A0 CLK (2.0)) (SETUP IO0 CLK (2.0)) (SETUP RW CLK (2.0)) (SETUP CE1 CLK (2.0)) (SETUP LBNeg CLK (2.0)) (SETUP CNTLDNeg CLK (2.0)) (SETUP CNTINCNeg CLK (2.0)) (SETUP CNTRSTNeg CLK (2.0)) (SETUP CNTRDNeg CLK (2.0)) (SETUP MKLDNeg CLK (2.0)) (SETUP MKLDNeg CLK (2.0)) (SETUP TDI TCK (2.0)) (HOLD A0 CLK (0.7)) (HOLD IO0 CLK (0.7)) (HOLD RW CLK (0.7)) (HOLD CE1 CLK (0.7)) (HOLD LBNeg CLK (0.7)) (HOLD CNTLDNeg CLK (0.7)) (HOLD CNTINCNeg CLK (0.7)) (HOLD CNTRSTNeg CLK (0.7)) (HOLD CNTRDNeg CLK (0.7)) (HOLD MKLDNeg CLK (0.7)) (HOLD MKLDNeg CLK (0.7)) (HOLD TDI TCK (0.7)) (RECOVERY MRSTNeg CLK (10.0)) (RECOVERY TRSTNeg TCK (50.0)) )) (CELL (CELLTYPE "VITALbuf" ) (INSTANCE %LABEL%/TCCS) (DELAY (ABSOLUTE ( DEVICE (9.0) ) ) )</TIMING></FMFTIME></BODY></FTML>⌨️ 快捷键说明
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