idt70v5378.vhd
来自「VHDL的ram和fifo model code 包含众多的厂家」· VHDL 代码 · 共 1,156 行 · 第 1/5 页
VHD
1,156 行
---------------------------------------------------------------------------------- File Name: idt70v5378.vhd---------------------------------------------------------------------------------- Copyright (C) 2003 Integrated Device Technology; http://www.idt.com/-- Developed and supported by Free Model Foundry; http://www.FreeModelFoundry.com---- This program is free software; you can redistribute it and/or modify-- it under the terms of the GNU General Public License version 2 as-- published by the Free Software Foundation.---- This VHDL model is provided on an "AS IS" basis and IDT makes absolutely no-- warranty with respect to the information contained herein. IDT DISCLAIMS-- AND CUSTOMER WAIVES ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE-- ENTIRE RISK AS TO QUALITY AND PERFORMANCE IS WITH THE USER ACCORDINGLY, IN-- NO EVENT SHALL IDT BE LIABLE FOR ANY DIRECT OR INDIRECT DAMAGES,WHETHER IN-- CONTRACT OR TORT, INCLUDING ANY LOST PROFITS OR OTHER INCIDENTAL,-- CONSEQUENTIAL, EXEMPLARY, OR PUNITIVE DAMAGES ARISING OUT OF THE USE OR-- APPLICATION OF THE VHDL model. Further, IDT reserves the right to make-- changes without notice to any product herein to improve reliability,-- function, or design. 營DT does not convey any license under patent rights-- or any other intellectual property rights, including those of third parties.-- IDT is not obligated to provide maintenance or support for the licensed VHDL-- model.------------------------------------------------------------------------------------ MODIFICATION HISTORY:---- version: | author: | mod date: | changes made:-- V1.0 M.Radmanovic 03 Oct 06 Inital Release------------------------------------------------------------------------------------ PART DESCRIPTION:---- Library: RAM-- Technology:-- Part: IDT70V5378---- Description: 32K x 18 Synchronous Four-Port Static RAM--------------------------------------------------------------------------------LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE STD.textio.ALL; USE IEEE.vital_timing.ALL; USE IEEE.vital_primitives.ALL;LIBRARY FMF; USE FMF.gen_utils.ALL; USE FMF.conversions.ALL;---------------------------------------------------------------------------------- ENTITY DECLARATION--------------------------------------------------------------------------------ENTITY idt70v5378 IS GENERIC ( -- tipd delays: interconnect path delays tipd_A0P1 : VitalDelayType01 := VitalZeroDelay01; tipd_A1P1 : VitalDelayType01 := VitalZeroDelay01; tipd_A2P1 : VitalDelayType01 := VitalZeroDelay01; tipd_A3P1 : VitalDelayType01 := VitalZeroDelay01; tipd_A4P1 : VitalDelayType01 := VitalZeroDelay01; tipd_A5P1 : VitalDelayType01 := VitalZeroDelay01; tipd_A6P1 : VitalDelayType01 := VitalZeroDelay01; tipd_A7P1 : VitalDelayType01 := VitalZeroDelay01; tipd_A8P1 : VitalDelayType01 := VitalZeroDelay01; tipd_A9P1 : VitalDelayType01 := VitalZeroDelay01; tipd_A10P1 : VitalDelayType01 := VitalZeroDelay01; tipd_A11P1 : VitalDelayType01 := VitalZeroDelay01; tipd_A12P1 : VitalDelayType01 := VitalZeroDelay01; tipd_A13P1 : VitalDelayType01 := VitalZeroDelay01; tipd_A14P1 : VitalDelayType01 := VitalZeroDelay01; tipd_A0P2 : VitalDelayType01 := VitalZeroDelay01; tipd_A1P2 : VitalDelayType01 := VitalZeroDelay01; tipd_A2P2 : VitalDelayType01 := VitalZeroDelay01; tipd_A3P2 : VitalDelayType01 := VitalZeroDelay01; tipd_A4P2 : VitalDelayType01 := VitalZeroDelay01; tipd_A5P2 : VitalDelayType01 := VitalZeroDelay01; tipd_A6P2 : VitalDelayType01 := VitalZeroDelay01; tipd_A7P2 : VitalDelayType01 := VitalZeroDelay01; tipd_A8P2 : VitalDelayType01 := VitalZeroDelay01; tipd_A9P2 : VitalDelayType01 := VitalZeroDelay01; tipd_A10P2 : VitalDelayType01 := VitalZeroDelay01; tipd_A11P2 : VitalDelayType01 := VitalZeroDelay01; tipd_A12P2 : VitalDelayType01 := VitalZeroDelay01; tipd_A13P2 : VitalDelayType01 := VitalZeroDelay01; tipd_A14P2 : VitalDelayType01 := VitalZeroDelay01; tipd_A0P3 : VitalDelayType01 := VitalZeroDelay01; tipd_A1P3 : VitalDelayType01 := VitalZeroDelay01; tipd_A2P3 : VitalDelayType01 := VitalZeroDelay01; tipd_A3P3 : VitalDelayType01 := VitalZeroDelay01; tipd_A4P3 : VitalDelayType01 := VitalZeroDelay01; tipd_A5P3 : VitalDelayType01 := VitalZeroDelay01; tipd_A6P3 : VitalDelayType01 := VitalZeroDelay01; tipd_A7P3 : VitalDelayType01 := VitalZeroDelay01; tipd_A8P3 : VitalDelayType01 := VitalZeroDelay01; tipd_A9P3 : VitalDelayType01 := VitalZeroDelay01; tipd_A10P3 : VitalDelayType01 := VitalZeroDelay01; tipd_A11P3 : VitalDelayType01 := VitalZeroDelay01; tipd_A12P3 : VitalDelayType01 := VitalZeroDelay01; tipd_A13P3 : VitalDelayType01 := VitalZeroDelay01; tipd_A14P3 : VitalDelayType01 := VitalZeroDelay01; tipd_A0P4 : VitalDelayType01 := VitalZeroDelay01; tipd_A1P4 : VitalDelayType01 := VitalZeroDelay01; tipd_A2P4 : VitalDelayType01 := VitalZeroDelay01; tipd_A3P4 : VitalDelayType01 := VitalZeroDelay01; tipd_A4P4 : VitalDelayType01 := VitalZeroDelay01; tipd_A5P4 : VitalDelayType01 := VitalZeroDelay01; tipd_A6P4 : VitalDelayType01 := VitalZeroDelay01; tipd_A7P4 : VitalDelayType01 := VitalZeroDelay01; tipd_A8P4 : VitalDelayType01 := VitalZeroDelay01; tipd_A9P4 : VitalDelayType01 := VitalZeroDelay01; tipd_A10P4 : VitalDelayType01 := VitalZeroDelay01; tipd_A11P4 : VitalDelayType01 := VitalZeroDelay01; tipd_A12P4 : VitalDelayType01 := VitalZeroDelay01; tipd_A13P4 : VitalDelayType01 := VitalZeroDelay01; tipd_A14P4 : VitalDelayType01 := VitalZeroDelay01; tipd_IO0P1 : VitalDelayType01 := VitalZeroDelay01; tipd_IO1P1 : VitalDelayType01 := VitalZeroDelay01; tipd_IO2P1 : VitalDelayType01 := VitalZeroDelay01; tipd_IO3P1 : VitalDelayType01 := VitalZeroDelay01; tipd_IO4P1 : VitalDelayType01 := VitalZeroDelay01; tipd_IO5P1 : VitalDelayType01 := VitalZeroDelay01; tipd_IO6P1 : VitalDelayType01 := VitalZeroDelay01; tipd_IO7P1 : VitalDelayType01 := VitalZeroDelay01; tipd_IO8P1 : VitalDelayType01 := VitalZeroDelay01; tipd_IO9P1 : VitalDelayType01 := VitalZeroDelay01; tipd_IO10P1 : VitalDelayType01 := VitalZeroDelay01; tipd_IO11P1 : VitalDelayType01 := VitalZeroDelay01; tipd_IO12P1 : VitalDelayType01 := VitalZeroDelay01; tipd_IO13P1 : VitalDelayType01 := VitalZeroDelay01; tipd_IO14P1 : VitalDelayType01 := VitalZeroDelay01; tipd_IO15P1 : VitalDelayType01 := VitalZeroDelay01; tipd_IO16P1 : VitalDelayType01 := VitalZeroDelay01; tipd_IO17P1 : VitalDelayType01 := VitalZeroDelay01; tipd_IO0P2 : VitalDelayType01 := VitalZeroDelay01; tipd_IO1P2 : VitalDelayType01 := VitalZeroDelay01; tipd_IO2P2 : VitalDelayType01 := VitalZeroDelay01; tipd_IO3P2 : VitalDelayType01 := VitalZeroDelay01; tipd_IO4P2 : VitalDelayType01 := VitalZeroDelay01; tipd_IO5P2 : VitalDelayType01 := VitalZeroDelay01; tipd_IO6P2 : VitalDelayType01 := VitalZeroDelay01; tipd_IO7P2 : VitalDelayType01 := VitalZeroDelay01; tipd_IO8P2 : VitalDelayType01 := VitalZeroDelay01; tipd_IO9P2 : VitalDelayType01 := VitalZeroDelay01; tipd_IO10P2 : VitalDelayType01 := VitalZeroDelay01; tipd_IO11P2 : VitalDelayType01 := VitalZeroDelay01; tipd_IO12P2 : VitalDelayType01 := VitalZeroDelay01; tipd_IO13P2 : VitalDelayType01 := VitalZeroDelay01; tipd_IO14P2 : VitalDelayType01 := VitalZeroDelay01; tipd_IO15P2 : VitalDelayType01 := VitalZeroDelay01; tipd_IO16P2 : VitalDelayType01 := VitalZeroDelay01; tipd_IO17P2 : VitalDelayType01 := VitalZeroDelay01; tipd_IO0P3 : VitalDelayType01 := VitalZeroDelay01; tipd_IO1P3 : VitalDelayType01 := VitalZeroDelay01; tipd_IO2P3 : VitalDelayType01 := VitalZeroDelay01; tipd_IO3P3 : VitalDelayType01 := VitalZeroDelay01; tipd_IO4P3 : VitalDelayType01 := VitalZeroDelay01; tipd_IO5P3 : VitalDelayType01 := VitalZeroDelay01; tipd_IO6P3 : VitalDelayType01 := VitalZeroDelay01; tipd_IO7P3 : VitalDelayType01 := VitalZeroDelay01; tipd_IO8P3 : VitalDelayType01 := VitalZeroDelay01; tipd_IO9P3 : VitalDelayType01 := VitalZeroDelay01; tipd_IO10P3 : VitalDelayType01 := VitalZeroDelay01; tipd_IO11P3 : VitalDelayType01 := VitalZeroDelay01; tipd_IO12P3 : VitalDelayType01 := VitalZeroDelay01; tipd_IO13P3 : VitalDelayType01 := VitalZeroDelay01; tipd_IO14P3 : VitalDelayType01 := VitalZeroDelay01; tipd_IO15P3 : VitalDelayType01 := VitalZeroDelay01; tipd_IO16P3 : VitalDelayType01 := VitalZeroDelay01; tipd_IO17P3 : VitalDelayType01 := VitalZeroDelay01; tipd_IO0P4 : VitalDelayType01 := VitalZeroDelay01; tipd_IO1P4 : VitalDelayType01 := VitalZeroDelay01; tipd_IO2P4 : VitalDelayType01 := VitalZeroDelay01; tipd_IO3P4 : VitalDelayType01 := VitalZeroDelay01; tipd_IO4P4 : VitalDelayType01 := VitalZeroDelay01; tipd_IO5P4 : VitalDelayType01 := VitalZeroDelay01; tipd_IO6P4 : VitalDelayType01 := VitalZeroDelay01; tipd_IO7P4 : VitalDelayType01 := VitalZeroDelay01; tipd_IO8P4 : VitalDelayType01 := VitalZeroDelay01; tipd_IO9P4 : VitalDelayType01 := VitalZeroDelay01; tipd_IO10P4 : VitalDelayType01 := VitalZeroDelay01; tipd_IO11P4 : VitalDelayType01 := VitalZeroDelay01; tipd_IO12P4 : VitalDelayType01 := VitalZeroDelay01; tipd_IO13P4 : VitalDelayType01 := VitalZeroDelay01; tipd_IO14P4 : VitalDelayType01 := VitalZeroDelay01; tipd_IO15P4 : VitalDelayType01 := VitalZeroDelay01; tipd_IO16P4 : VitalDelayType01 := VitalZeroDelay01; tipd_IO17P4 : VitalDelayType01 := VitalZeroDelay01; tipd_CLKP1 : VitalDelayType01 := VitalZeroDelay01; tipd_CLKP2 : VitalDelayType01 := VitalZeroDelay01; tipd_CLKP3 : VitalDelayType01 := VitalZeroDelay01; tipd_CLKP4 : VitalDelayType01 := VitalZeroDelay01; tipd_MRSTNeg : VitalDelayType01 := VitalZeroDelay01; tipd_RWP1 : VitalDelayType01 := VitalZeroDelay01; tipd_RWP2 : VitalDelayType01 := VitalZeroDelay01; tipd_RWP3 : VitalDelayType01 := VitalZeroDelay01; tipd_RWP4 : VitalDelayType01 := VitalZeroDelay01; tipd_CE0P1Neg : VitalDelayType01 := VitalZeroDelay01; tipd_CE0P2Neg : VitalDelayType01 := VitalZeroDelay01; tipd_CE0P3Neg : VitalDelayType01 := VitalZeroDelay01; tipd_CE0P4Neg : VitalDelayType01 := VitalZeroDelay01; tipd_CE1P1 : VitalDelayType01 := VitalZeroDelay01; tipd_CE1P2 : VitalDelayType01 := VitalZeroDelay01; tipd_CE1P3 : VitalDelayType01 := VitalZeroDelay01; tipd_CE1P4 : VitalDelayType01 := VitalZeroDelay01; tipd_OEP1Neg : VitalDelayType01 := VitalZeroDelay01; tipd_OEP2Neg : VitalDelayType01 := VitalZeroDelay01; tipd_OEP3Neg : VitalDelayType01 := VitalZeroDelay01; tipd_OEP4Neg : VitalDelayType01 := VitalZeroDelay01; tipd_UBP1Neg : VitalDelayType01 := VitalZeroDelay01; tipd_UBP2Neg : VitalDelayType01 := VitalZeroDelay01; tipd_UBP3Neg : VitalDelayType01 := VitalZeroDelay01; tipd_UBP4Neg : VitalDelayType01 := VitalZeroDelay01; tipd_LBP1Neg : VitalDelayType01 := VitalZeroDelay01; tipd_LBP2Neg : VitalDelayType01 := VitalZeroDelay01; tipd_LBP3Neg : VitalDelayType01 := VitalZeroDelay01; tipd_LBP4Neg : VitalDelayType01 := VitalZeroDelay01; tipd_CNTLDP1Neg : VitalDelayType01 := VitalZeroDelay01; tipd_CNTLDP2Neg : VitalDelayType01 := VitalZeroDelay01; tipd_CNTLDP3Neg : VitalDelayType01 := VitalZeroDelay01; tipd_CNTLDP4Neg : VitalDelayType01 := VitalZeroDelay01; tipd_CNTINCP1Neg : VitalDelayType01 := VitalZeroDelay01; tipd_CNTINCP2Neg : VitalDelayType01 := VitalZeroDelay01; tipd_CNTINCP3Neg : VitalDelayType01 := VitalZeroDelay01; tipd_CNTINCP4Neg : VitalDelayType01 := VitalZeroDelay01; tipd_CNTRDP1Neg : VitalDelayType01 := VitalZeroDelay01; tipd_CNTRDP2Neg : VitalDelayType01 := VitalZeroDelay01; tipd_CNTRDP3Neg : VitalDelayType01 := VitalZeroDelay01; tipd_CNTRDP4Neg : VitalDelayType01 := VitalZeroDelay01; tipd_CNTRSTP1Neg : VitalDelayType01 := VitalZeroDelay01; tipd_CNTRSTP2Neg : VitalDelayType01 := VitalZeroDelay01; tipd_CNTRSTP3Neg : VitalDelayType01 := VitalZeroDelay01; tipd_CNTRSTP4Neg : VitalDelayType01 := VitalZeroDelay01;⌨️ 快捷键说明
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