cy7c1325.vhd

来自「VHDL的ram和fifo model code 包含众多的厂家」· VHDL 代码 · 共 1,415 行 · 第 1/4 页

                    TimingData      => TD_BWAN_CLK,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_BWAN_CLK );

                VitalSetupHoldCheck (
                    TestSignal      => ADVNIn,
                    TestSignalName  => "ADV",
                    RefSignal       => CLKIn,
                    RefSignalName   => "CLK",
                    SetupHigh       => tsetup_ADVNeg_CLK,
                    SetupLow        => tsetup_ADVNeg_CLK,
                    HoldHigh        => thold_ADVNeg_CLK,
                    HoldLow         => thold_ADVNeg_CLK,
                    CheckEnabled    => (ZZIn ='0'),
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_ADVNIn_CLK,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_ADVNIn_CLK );

                VitalSetupHoldCheck (
                    TestSignal      => ADSPNIn,
                    TestSignalName  => "ADSP",
                    RefSignal       => CLKIn,
                    RefSignalName   => "CLK",
                    SetupHigh       => tsetup_ADSCNeg_CLK,
                    SetupLow        => tsetup_ADSCNeg_CLK,
                    HoldHigh        => thold_ADSCNeg_CLK,
                    HoldLow         => thold_ADSCNeg_CLK,
                    CheckEnabled    => (ZZIn ='0'),
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_ADSPNIn_CLK,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_ADSPNIn_CLK );

                VitalSetupHoldCheck (
                    TestSignal      => ADSCNIn,
                    TestSignalName  => "ADSC",
                    RefSignal       => CLKIn,
                    RefSignalName   => "CLK",
                    SetupHigh       => tsetup_ADSCNeg_CLK,
                    SetupLow        => tsetup_ADSCNeg_CLK,
                    HoldHigh        => thold_ADSCNeg_CLK,
                    HoldLow         => thold_ADSCNeg_CLK,
                    CheckEnabled    => (ZZIn ='0'),
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_ADSCNIn_CLK,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_ADSCNIn_CLK );

                VitalSetupHoldCheck (
                    TestSignal      => CE1NegIn,
                    TestSignalName  => "CE1Neg",
                    RefSignal       => CLKIn,
                    RefSignalName   => "CLK",
                    SetupHigh       => tsetup_CE2_CLK,
                    SetupLow        => tsetup_CE2_CLK,
                    HoldHigh        => thold_CE2_CLK,
                    HoldLow         => thold_CE2_CLK,
                    CheckEnabled    => (ZZIn ='0'),
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_CE1NegIn_CLK,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_CE1NegIn_CLK );

                VitalSetupHoldCheck (
                    TestSignal      => CE3NegIn,
                    TestSignalName  => "CE3Neg",
                    RefSignal       => CLKIn,
                    RefSignalName   => "CLK",
                    SetupHigh       => tsetup_CE2_CLK,
                    SetupLow        => tsetup_CE2_CLK,
                    HoldHigh        => thold_CE2_CLK,
                    HoldLow         => thold_CE2_CLK,
                    CheckEnabled    => (ZZIn ='0'),
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_CE3NegIn_CLK,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_CE3NegIn_CLK );

                VitalSetupHoldCheck (
                    TestSignal      => CE2In,
                    TestSignalName  => "CE2",
                    RefSignal       => CLKIn,
                    RefSignalName   => "CLK",
                    SetupHigh       => tsetup_CE2_CLK,
                    SetupLow        => tsetup_CE2_CLK,
                    HoldHigh        => thold_CE2_CLK,
                    HoldLow         => thold_CE2_CLK,
                    CheckEnabled    => (ZZIn ='0'),
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_CE2In_CLK,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_CE2In_CLK );

                VitalPeriodPulseCheck (
                    TestSignal      =>  CLKIn,
                    TestSignalName  =>  "CLK",
                    Period          =>  tperiod_CLK_posedge,
                    PulseWidthLow   =>  tpw_CLK_negedge,
                    PulseWidthHigh  =>  tpw_CLK_posedge,
                    PeriodData      =>  PD_CLK,
                    XOn             =>  XOn,
                    MsgOn           =>  MsgOn,
                    Violation       =>  Pviol_CLK,
                    HeaderMsg       =>  InstancePath & PartID,
                    CheckEnabled    =>  (ZZIn ='0') );

                Violation := Pviol_CLK          OR Tviol_DatAIn_CLK    OR
                             Tviol_DatBIn_CLK   OR Tviol_AddressIn_CLK OR
                             Tviol_ADSCNIn_CLK  OR Tviol_CE2In_CLK     OR
                             Tviol_CE3NegIn_CLK OR Tviol_CE1NegIn_CLK  OR
                             Tviol_ADVNIn_CLK   OR Tviol_ADSPNIn_CLK   OR
                             Tviol_BWAN_CLK     OR Tviol_BWBN_CLK      OR
                             Tviol_BWEN_CLK     OR Tviol_GWN_CLK;

                ASSERT Violation = '0'
                    REPORT InstancePath & partID & ": simulation may be" &
                           " inaccurate due to timing violations"
                    SEVERITY SeverityMode;

            END IF;

    ----------------------------------------------------------------------------
    -- Functional Section
    ----------------------------------------------------------------------------

    IF rising_edge(CLKIn) AND (ZZIn = '0') AND zz_reset THEN
        ASSERT (not(Is_X(BWANIn)))
            REPORT InstancePath & partID & ": Unusable value for BWAN"
            SEVERITY SeverityMode;
        ASSERT (not(Is_X(BWBNIn)))
            REPORT InstancePath & partID & ": Unusable value for BWBN"
            SEVERITY SeverityMode;
        ASSERT (not(Is_X(GWNIn)))
            REPORT InstancePath & partID & ": Unusable value for GWN"
            SEVERITY SeverityMode;
        ASSERT (not(Is_X(BWENIn)))
            REPORT InstancePath & partID & ": Unusable value for BWEN"
            SEVERITY SeverityMode;
        ASSERT (not(Is_X(ADVNIn)))
            REPORT InstancePath & partID & ": Unusable value for ADVN"
            SEVERITY SeverityMode;
        ASSERT (not(Is_X(ADSPNIn)))
            REPORT InstancePath & partID & ": Unusable value for ADSPN"
            SEVERITY SeverityMode;
        ASSERT (not(Is_X(ADSCNIn)))
            REPORT InstancePath & partID & ": Unusable value for ADSCN"
            SEVERITY SeverityMode;
        ASSERT (not(Is_X(CE2In)))
            REPORT InstancePath & partID & ": Unusable value for CE2"
            SEVERITY SeverityMode;
        ASSERT (not(Is_X(CE1NegIn)))
            REPORT InstancePath & partID & ": Unusable value for CE1Neg"
            SEVERITY SeverityMode;
        ASSERT (not(Is_X(CE3NegIn)))
            REPORT InstancePath & partID & ": Unusable value for CE3Neg"
            SEVERITY SeverityMode;

        -- Command Decode
        IF (GWNIn = '1' AND (BWENIn = '1' OR (BWENIn = '0' AND
            BWANIn = '1' AND BWBNIn = '1' ))) THEN
            R := '1';
        ELSE
            R := '0';
        END IF;

        IF ((CE3NegIn = '1' AND CE1NegIn = '0') AND (ADSPNIn = '0' OR
            (ADSPNIn = '1' AND ADSCNIn = '0'))) OR
            (CE1NegIn = '1' AND ADSCNIn = '0') OR
            ((CE2In = '0' AND CE1NegIn = '0') AND (ADSPNIn = '0' OR
            (ADSPNIn = '1' AND ADSCNIn = '0'))) THEN
            command := ds;
        ELSIF ((CE3NegIn = '0' AND CE2In = '1' AND CE1NegIn = '0')
            AND (ADSPNIn = '0' OR (ADSPNIn = '1' AND ADSCNIn = '0'))
            AND R = '1') THEN
            command := begin_read;
        ELSIF (ADSCNIn = '1' AND (ADSPNIn = '1' OR CE1NegIn = '1')
            AND R = '1') THEN
            IF ADVNIn = '0' THEN
                command := read_burst;
            ELSE
                command := read_susp;
            END IF;
        ELSIF (CE3NegIn = '0' AND CE2In = '1' AND CE1NegIn = '0'
            AND ADSPNIn = '0' AND R = '0') THEN
            command := begin_SPwr;
        ELSIF (ADSCNIn = '1' AND (ADSPNIn = '1' OR CE1NegIn = '1')
            AND R = '0') THEN
            IF ADVNIn = '0' THEN
                command := SPwr_burst;
            ELSE
                command := SPwr_susp;
            END IF;
        ELSIF (CE3NegIn = '0' AND CE2In = '1' AND CE1NegIn = '0' AND
            ADSPNIn = '1' AND ADSCNIn = '0' AND R = '0') THEN
            command := SCwr;
        ELSE
            ASSERT false
                REPORT InstancePath & partID & ": Could not decode "
                       & "command."
                SEVERITY SeverityMode;
        END IF;

        -- The State Machine
        CASE state IS
            WHEN desel =>
                CASE command IS

                    WHEN begin_SPwr =>
                        state <= begin_SPwrite;
                        MemAddr := to_nat(AddressIn);
                        startaddr := MemAddr;
                        memstart := to_nat(AddressIn(1 downto 0));
                        ReadMem(MemAddr);

                    WHEN begin_read =>
                        state <= begin_rd;
                        MemAddr := to_nat(AddressIn);
                        startaddr := MemAddr;
                        memstart := to_nat(AddressIn(1 downto 0));
                        ReadMem(MemAddr);

                    WHEN SCwr =>
                        state <= SCwrite;
                        MemAddr := to_nat(AddressIn);
                        startaddr := MemAddr;
                        memstart := to_nat(AddressIn(1 downto 0));
                        OBuf1 := (others => 'Z');
                        WriteMem(
                            WAddr  => MemAddr,
                            WDatA  => DatAIn,
                            WDatB  => DatBIn,
                            WGWN   => GWNIn,
                            WBWA   => BWANIn,
                            WBWB   => BWBNIn);

                    WHEN others =>
                        null;

                END CASE;

            WHEN begin_rd =>
                Burst_Cnt := 0;
                CASE command IS
                    WHEN ds =>
                        state <= desel;
                        OBuf1 := (others => 'Z');

                    WHEN begin_SPwr =>
                        state <= begin_SPwrite;
                        MemAddr := to_nat(AddressIn);
                        startaddr := MemAddr;
                        memstart := to_nat(AddressIn(1 downto 0));
                        ReadMem(MemAddr);

                    WHEN begin_read =>
                        MemAddr := to_nat(AddressIn);
                        startaddr := MemAddr;
                        memstart := to_nat(AddressIn(1 downto 0));
                        ReadMem(MemAddr);

                    WHEN SCwr =>
                        state <= SCwrite;
                        MemAddr := to_nat(AddressIn);
                        startaddr := MemAddr;
                        memstart := to_nat(AddressIn(1 downto 0));
                        OBuf1 := (others => 'Z');
                        WriteMem(
                            WAddr  => MemAddr,
                            WDatA  => DatAIn,
                            WDatB  => DatBIn,
                            WGWN   => GWNIn,
                            WBWA   => BWANIn,
                            WBWB   => BWBNIn);

                    WHEN SPwr_burst =>
                        OBuf1 := (others => 'Z');

                    WHEN SPwr_susp =>
                        state <= SPwrite;
                        OBuf1 := (others => 'Z');
                        WriteMem(
                            WAddr  => MemAddr,
                            WDatA  => DatAIn,
                            WDatB  => DatBIn,
                            WGWN   => GWNIn,
                            WBWA   => BWANIn,
                            WBWB   => BWBNIn);

                    WHEN read_burst =>
                        state <= read;
                        Burst_Cnt := Burst_Cnt + 1;
                        offset := Burst_Seq(memstart)(Burst_Cnt);
                        MemAddr := startaddr + offset;
                        ReadMem(MemAddr);

                    WHEN read_susp =>
                        OBuf1 := (others => 'Z');

                END CASE;

            WHEN begin_SPwrite =>
                Burst_Cnt := 0;
                CASE command IS
                    WHEN ds =>
                        state <= desel;
                        OBuf1 := (others => 'Z');

                    WHEN begin_SPwr =>
                        WriteMem(
                            WAddr  => MemAddr,
                            WDatA  => DatAIn,
                            WDatB  => DatBIn,
                            WGWN   => GWNIn,
                            WBWA   => BWANIn,
                            WBWB   => BWBNIn);
                        MemAddr := to_nat(AddressIn);
                        startaddr := MemAddr;
                        memstart := to_nat(AddressIn(1 downto 0));

                    WHEN begin_read =>
                        state <= begin_rd;
                        MemAddr := to_nat(AddressIn);
                        startaddr := MemAddr;
                        memstart := to_nat(AddressIn(1 downto 0));
                        ReadMem(MemAddr);

                    WHEN SCwr =>
                        state <= SCwrite;
                        WriteMem(
                            WAddr  => MemAddr,
                            WDatA  => DatAIn,
                            WDatB  => DatBIn,
                            WGWN   => GWNIn,
                            WBWA   => BWANIn,
                            WBWB   => BWBNIn);

                    WHEN SPwr_burst =>
                        OBuf1 := (others => 'Z');

                    WHEN SPwr_susp =>