mt48lc4m16.vhd

来自「VHDL的ram和fifo model code 包含众多的厂家」· VHDL 代码 · 共 1,475 行 · 第 1/5 页

                    written := true;

                ELSIF (cur_bank = bank) OR (command = mrs) THEN
                    ASSERT false
                        REPORT InstancePath & partID & BankString &
                               ": Illegal command "
                               & "received in active state."
                        SEVERITY SeverityMode;
                END IF;

            WHEN write =>
                IF (command = bst) THEN
                    IF rising_edge(CLKIn) THEN
                        ASSERT false
                            REPORT InstancePath & partID & BankString &
                               ": Illegal command "
                               & "received in write state."
                            SEVERITY SeverityMode;
                    END IF;
                ELSIF (command = read) THEN
                    IF cur_bank = bank THEN

                        FixColumnAddress(bank);

                        ReadFromMem(bank);

                        Burst_Cnt(bank) := 1;
                        IF (AddressIn(10) = '0') THEN
                            statebank(bank) <= read;
                        ELSIF (AddressIn(10) = '1') THEN
                            statebank(bank) <= read_auto_pre;
                        END IF;
                    ELSE
                        statebank(bank) <= bank_act;
                    END IF;
                ELSIF (command = writ) THEN
                    IF (Burst_Cnt(bank) = Burst_Length) THEN
                        statebank(bank) <= bank_act;
                        Burst_Cnt(bank) := 0;
                        ras_in(bank) <= '1';
                        Burst_Inc(bank) := 0;
                    ELSE
                        IF cur_bank = bank THEN

                            FixColumnAddress(bank);

                            ASSERT ((AddressIn(10) = '0') OR
                                    (AddressIn(10) = '1'))
                                REPORT InstancePath & partID & BankString &
                                  ": AddressIn(10) = X"
                                  & " during write command. Next state unknown."
                                SEVERITY SeverityMode;
                            IF (AddressIn(10) = '0') THEN
                                statebank(bank) <= write;
                            ELSIF (AddressIn(10) = '1') THEN
                                statebank(bank) <= write_auto_pre;
                            END IF;

                            WriteToMem(bank);

                            Burst_Cnt(bank) := 1;
                            written := true;
                        ELSE
                            statebank(bank)<=bank_act;
                        END IF;
                    END IF;

                ELSIF (command = pre) AND ((cur_bank = bank) OR
                            (AddressIn(10) = '1')) THEN
                    ASSERT ras_out(bank) = '1'
                        REPORT InstancePath & partID & BankString &
                               ": precharge command"
                               & " does not meet tRAS time."
                        SEVERITY SeverityMode;
                   ASSERT (DQML_nwv = '1' and DQMH_nwv = '1')
                       REPORT InstancePath & partID & BankString &
                          ": DQM should be"
                          & " held high, data is lost."
                       SEVERITY SeverityMode;
                   statebank(bank) <= precharge, idle AFTER tdevice_TRP;
                ELSIF (command = nop) OR (cur_bank /= bank) THEN
                    IF (Burst_Cnt(bank) = Burst_Length OR WB = single) THEN
                         statebank(bank) <= bank_act;
                         Burst_Cnt(bank) := 0;
                         ras_in(bank) <= '1';
                         Burst_Inc(bank) := 0;
                    ELSE
                         statebank(bank) <= write;

                         BurstCtrl(bank);

                         WriteToMem(bank);

                    END IF;
                ELSIF cur_bank = bank THEN
                    ASSERT false
                        REPORT InstancePath & partID & ": Illegal command"
                               & " received in write state."
                        SEVERITY SeverityMode;
                END IF;

            WHEN read =>
                IF (command = bst) THEN
                    statebank(bank) <= bank_act;
                    Burst_Cnt(bank) := 0;
                    Burst_Inc(bank) := 0;
                ELSIF (command = read) THEN
                    IF cur_bank = bank THEN

                        FixColumnAddress(bank);

                        ReadFromMem(bank);

                        Burst_Cnt(bank) := 1;
                        IF (AddressIn(10) = '0') THEN
                            statebank(bank) <= read;
                        ELSIF (AddressIn(10) = '1') THEN
                            statebank(bank) <= read_auto_pre;
                        END IF;
                    ELSE
                        statebank(bank) <= bank_act;
                    END IF;
                ELSIF (command = writ) THEN
                    IF cur_bank = bank THEN
                        IF (Burst_Cnt(bank) = Burst_Length) THEN
                            statebank(bank) <= bank_act;
                            Burst_Cnt(bank) := 0;
                            ras_in(bank) <= '1';
                            Burst_Inc(bank) := 0;
                        ELSE

                            FixColumnAddress(bank);

                            WriteToMem(bank);

                            ASSERT ((AddressIn(10) = '0') OR
                                    (AddressIn(10) = '1'))
                                REPORT InstancePath & partID & BankString &
                                    ": AddressIn(10) = X"
                                & " during write command. Next state unknown."
                                SEVERITY SeverityMode;
                            IF (AddressIn(10) = '0') THEN
                                statebank(bank) <= write;
                            ELSIF (AddressIn(10) = '1') THEN
                                statebank(bank) <= write_auto_pre;
                            END IF;
                            Burst_Cnt(bank) := 1;
                            written := true;
                        END IF;
                    ELSE
                        statebank(bank)<=bank_act;
                    END IF;
                ELSIF (command = pre) AND ((cur_bank = bank) OR
                       (AddressIn(10) = '1')) THEN
                    statebank(bank) <= precharge, idle AFTER tdevice_TRP;
                    ASSERT ras_out(bank) = '1'
                        REPORT InstancePath & partID & BankString &
                           ": precharge command"
                               & " does not meet tRAS time."
                        SEVERITY SeverityMode;
                ELSIF (command = nop) OR (cur_bank /= bank) THEN
                    IF (Burst_Cnt(bank) = Burst_Length) THEN
                        statebank(bank) <= bank_act;
                        Burst_Cnt(bank) := 0;
                        ras_in(bank) <= '1';
                        Burst_Inc(bank) := 0;
                    ELSE
                        statebank(bank) <= read;

                        BurstCtrl(bank);

                        ReadFromMem(bank);

                    END IF;
                ELSIF cur_bank = bank THEN
                    ASSERT false
                        REPORT InstancePath & partID & BankString &
                               ": Illegal command"
                               & " received in read state."
                        SEVERITY SeverityMode;
                END IF;

            WHEN write_auto_pre =>
                IF (command = nop) OR (cur_bank /= bank) THEN
                    IF (Burst_Cnt(bank) = Burst_Length OR WB = single) THEN
                        statebank(bank) <= precharge, idle AFTER tdevice_TRP;
                        Burst_Cnt(bank) := 0;
                        ras_in(bank) <= '1';
                        Burst_Inc(bank) := 0;
                    ELSE
                        statebank(bank)<=write_auto_pre;

                        BurstCtrl(bank);

                        WriteToMem(bank);

                    END IF;
               ELSE
                    ASSERT false
                        REPORT InstancePath & partID & BankString &
                               ": Illegal command"
                               & " received in write state."
                        SEVERITY SeverityMode;
                END IF;

            WHEN read_auto_pre =>
                IF (command = nop) OR (cur_bank /= bank) THEN
                    IF (Burst_Cnt(bank) = Burst_Length) THEN
                        statebank(bank) <= precharge, idle AFTER tdevice_TRP;
                        Burst_Cnt(bank) := 0;
                        ras_in(bank) <= '1';
                        Burst_Inc(bank) := 0;
                    ELSE
                        statebank(bank) <=read_auto_pre;

                        BurstCtrl(bank);

                        ReadFromMem(bank);

                    END IF;
                ELSIF (command = read) AND (cur_bank /= bank) THEN
                    statebank(bank) <= precharge, idle AFTER tdevice_TRP;
                ELSE
                    ASSERT false
                        REPORT InstancePath & partID & BankString &
                               ": Illegal command"
                               & " received in read state."
                        SEVERITY SeverityMode;
                END IF;

            WHEN others => null;
        END CASE;
        END LOOP banks;

    -- Check Refresh Status
        IF (written = true) THEN
            ASSERT Ref_Cnt > 0
                REPORT InstancePath & partID &
                       ": memory not refreshed (by ref_cnt)"
                SEVERITY SeverityMode;
        END IF;

    END IF;

    --------------------------------------------------------------------
    -- Output Section
    --------------------------------------------------------------------
    IF rising_edge(CLKIn) THEN
        DQML_reg2 := DQML_reg1;
        DQML_reg1 := DQMLIn;
        DQMH_reg2 := DQMH_reg1;
        DQMH_reg1 := DQMHIn;
        IF (CAS_Lat = 2) THEN
            DataDriveOutL := DataDrive2L;
            DataDriveOutH := DataDrive2H;
        ELSE
            DataDriveOutL := DataDrive3L;
            DataDriveOutH := DataDrive3H;
        END IF;

        IF DQML_reg2 = '1' THEN
            D_zd(7 downto 0) <= (OTHERS => 'Z');
        ELSE
            D_zd(7 downto 0) <= DataDriveOutL;
        END IF;
        IF DQMH_reg2 = '1' THEN
            D_zd(15 downto 8) <= (OTHERS => 'Z');
        ELSE
            D_zd(15 downto 8) <= DataDriveOutH;
        END IF;
        IF  CKEreg = '1' THEN
            DataDrive3L := DataDrive2L;
            DataDrive2L := DataDrive1L;
            DataDrive1L := DataDriveL;
            DataDrive3H := DataDrive2H;
            DataDrive2H := DataDrive1H;
            DataDrive1H := DataDriveH;
        END IF;
    END IF;

   -- The Powering-down State Machine
    IF (rising_edge(CLKIn) AND CKEreg = '1' AND CKEIn = '0') THEN

        ASSERT (not(Is_X(CSNegIn)))
            REPORT InstancePath & partID & ": Unusable value for CSNeg"
            SEVERITY SeverityMode;

        IF (CSNegIn = '1') THEN
            command := nop;
        END IF;

        CASE statebank(cur_bank) IS
            WHEN idle =>
                IF (command = nop) THEN