mt48lc4m16.vhd

来自「VHDL的ram和fifo model code 包含众多的厂家」· VHDL 代码 · 共 1,475 行 · 第 1/5 页

            -- Functionality Results Variables
            VARIABLE Violation  : X01 := '0';

            VARIABLE DataDriveOutL :  std_logic_vector(7 DOWNTO 0)
                                   := (OTHERS => 'Z');
            --Data out pipeline (CAS Latency)
            VARIABLE DataDriveL  : OutWord;
            VARIABLE DataDrive1L : OutWord;
            VARIABLE DataDrive2L : OutWord;
            VARIABLE DataDrive3L : OutWord;

            VARIABLE DataDriveOutH :  std_logic_vector(7 DOWNTO 0)
                                   := (OTHERS => 'Z');
            --Data out pipeline (CAS Latency)
            VARIABLE DataDriveH  : OutWord;
            VARIABLE DataDrive1H : OutWord;
            VARIABLE DataDrive2H : OutWord;
            VARIABLE DataDrive3H : OutWord;

            --DQM Output enable pipeline
            VARIABLE DQML_reg1   : std_logic := '1';
            VARIABLE DQML_reg2   : std_logic := '1';
            VARIABLE DQMH_reg1   : std_logic := '1';
            VARIABLE DQMH_reg2   : std_logic := '1';

        PROCEDURE FixColumnAddress( bank : IN NATURAL RANGE 0 TO 3) IS
        BEGIN
            MemAddr(bank)(HiColBit downto 0) := (others => '0');
            MemAddr(bank)(HiColBit downto Burst_Bits) :=
                      AddressIn(HiColBit downto Burst_Bits); --
            IF (Burst_Bits > 0) THEN
                Burst_Inc(bank) :=
                         to_nat(AddressIn(Burst_Bits-1 downto 0));
            END IF;
            StartAddr(bank) := Burst_Inc(bank) mod 8;
            BaseLoc(bank) := to_nat(MemAddr(bank));
            Location := BaseLoc(bank) + Burst_Inc(bank);
        END PROCEDURE ;

        PROCEDURE ReadFromMem( bank : IN NATURAL RANGE 0 TO 3) IS
        BEGIN
            IF MemDataL(Bank)(Location) = -2 THEN
                DataDriveL := (others => 'U');
            ELSIF MemDataL(Bank)(Location) = -1 THEN
                DataDriveL := (others => 'X');
            ELSE
                DataDriveL:=
                    to_slv(MemDataL(Bank)(Location),8);
            END IF;
            IF MemDataH(Bank)(Location) = -2 THEN
                DataDriveH := (others => 'U');
            ELSIF MemDataH(Bank)(Location) = -1 THEN
                DataDriveH := (others => 'X');
            ELSE
                DataDriveH:=
                    to_slv(MemDataH(Bank)(Location),8);
            END IF;
        END;

        PROCEDURE WriteToMem( bank : IN NATURAL RANGE 0 TO 3) IS
        BEGIN
            IF DQMLIn = '0' THEN
                IF Violation = '0' THEN
                    MemDataL(Bank)(Location) :=
                        to_nat(DataIn(7 downto 0));
                ELSE
                    MemDataL(Bank)(Location) := -1;
                END IF;
            END IF;
            IF DQMHIn = '0' THEN
                IF Violation = '0' THEN
                    MemDataH(Bank)(Location) :=
                        to_nat(DataIn(15 downto 8));
                ELSE
                    MemDataH(Bank)(Location) := -1;
                END IF;
            END IF;
        END;

        PROCEDURE BurstCtrl( bank : IN NATURAL RANGE 0 TO 3) IS
        BEGIN
            IF (Burst = sequential) THEN
                Burst_Inc(bank) := (Burst_Inc(bank) + 1) MOD
                                    Burst_Length;
            ELSE
                Burst_Inc(bank) := intab(StartAddr(bank))
                                        (Burst_Cnt(bank));
            END IF;
            Location := BaseLoc(bank) + Burst_Inc(bank);
            Burst_Cnt(bank) := Burst_Cnt(bank) + 1;
        END;

        BEGIN
            --------------------------------------------------------------------
            -- Timing Check Section
            --------------------------------------------------------------------
            IF (TimingChecksOn) THEN

                VitalSetupHoldCheck (
                    TestSignal      => BAIn,
                    TestSignalName  => "BA",
                    RefSignal       => CLKIn,
                    RefSignalName   => "CLK",
                    SetupHigh       => tsetup_A0_CLK,
                    SetupLow        => tsetup_A0_CLK,
                    HoldHigh        => thold_A0_CLK,
                    HoldLow         => thold_A0_CLK,
                    CheckEnabled    => chip_en,
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_BA_CLK,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_BA_CLK );

                VitalSetupHoldCheck (
                    TestSignal      => DataIn,
                    TestSignalName  => "Data",
                    RefSignal       => CLKIn,
                    RefSignalName   => "CLK",
                    SetupHigh       => tsetup_DQ0_CLK,
                    SetupLow        => tsetup_DQ0_CLK,
                    HoldHigh        => thold_DQ0_CLK,
                    HoldLow         => thold_DQ0_CLK,
                    CheckEnabled    => chip_en AND
                                        NOT(DataIn(0)='X' AND D_zd(0)='Z'),
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_D0_CLK,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_D0_CLK );

                VitalSetupHoldCheck (
                    TestSignal      => CKEIn,
                    TestSignalName  => "CKE",
                    RefSignal       => CLKIn,
                    RefSignalName   => "CLK",
                    SetupHigh       => tsetup_CKE_CLK,
                    SetupLow        => tsetup_CKE_CLK,
                    HoldHigh        => thold_CKE_CLK,
                    HoldLow         => thold_CKE_CLK,
                    CheckEnabled    => true,
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_CKE_CLK,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_CKE_CLK );

                VitalSetupHoldCheck (
                    TestSignal      => AddressIn,
                    TestSignalName  => "Address",
                    RefSignal       => CLKIn,
                    RefSignalName   => "CLK",
                    SetupHigh       => tsetup_A0_CLK,
                    SetupLow        => tsetup_A0_CLK,
                    HoldHigh        => thold_A0_CLK,
                    HoldLow         => thold_A0_CLK,
                    CheckEnabled    => chip_en,
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_Address_CLK,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_Address_CLK );

                VitalSetupHoldCheck (
                    TestSignal      => WENegIn,
                    TestSignalName  => "WENeg",
                    RefSignal       => CLKIn,
                    RefSignalName   => "CLK",
                    SetupHigh       => tsetup_CSNeg_CLK,
                    SetupLow        => tsetup_CSNeg_CLK,
                    HoldHigh        => thold_CSNeg_CLK,
                    HoldLow         => thold_CSNeg_CLK,
                    CheckEnabled    => chip_en,
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_WENeg_CLK,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_WENeg_CLK );

                VitalSetupHoldCheck (
                    TestSignal      => RASNegIn,
                    TestSignalName  => "RASNeg",
                    RefSignal       => CLKIn,
                    RefSignalName   => "CLK",
                    SetupHigh       => tsetup_CSNeg_CLK,
                    SetupLow        => tsetup_CSNeg_CLK,
                    HoldHigh        => thold_CSNeg_CLK,
                    HoldLow         => thold_CSNeg_CLK,
                    CheckEnabled    => chip_en,
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_RASNeg_CLK,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_RASNeg_CLK );

                VitalSetupHoldCheck (
                    TestSignal      => CSNegIn,
                    TestSignalName  => "CSNeg",
                    RefSignal       => CLKIn,
                    RefSignalName   => "CLK",
                    SetupHigh       => tsetup_CSNeg_CLK,
                    SetupLow        => tsetup_CSNeg_CLK,
                    HoldHigh        => thold_CSNeg_CLK,
                    HoldLow         => thold_CSNeg_CLK,
                    CheckEnabled    => chip_en,
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_CSNeg_CLK,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_CSNeg_CLK );

                VitalSetupHoldCheck (
                    TestSignal      => CASNegIn,
                    TestSignalName  => "CASNeg",
                    RefSignal       => CLKIn,
                    RefSignalName   => "CLK",
                    SetupHigh       => tsetup_CSNeg_CLK,
                    SetupLow        => tsetup_CSNeg_CLK,
                    HoldHigh        => thold_CSNeg_CLK,
                    HoldLow         => thold_CSNeg_CLK,
                    CheckEnabled    => chip_en,
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_CASNeg_CLK,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_CASNeg_CLK );

                VitalSetupHoldCheck (
                    TestSignal      => DQMLIn,
                    TestSignalName  => "DQML",
                    RefSignal       => CLKIn,
                    RefSignalName   => "CLK",
                    SetupHigh       => tsetup_CSNeg_CLK,
                    SetupLow        => tsetup_CSNeg_CLK,
                    HoldHigh        => thold_CSNeg_CLK,
                    HoldLow         => thold_CSNeg_CLK,
                    CheckEnabled    => chip_en,
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_DQML_CLK,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_DQML_CLK );

                VitalSetupHoldCheck (
                    TestSignal      => DQMHIn,
                    TestSignalName  => "DQMH",
                    RefSignal       => CLKIn,
                    RefSignalName   => "CLK",
                    SetupHigh       => tsetup_CSNeg_CLK,
                    SetupLow        => tsetup_CSNeg_CLK,
                    HoldHigh        => thold_CSNeg_CLK,
                    HoldLow         => thold_CSNeg_CLK,
                    CheckEnabled    => chip_en,
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_DQMH_CLK,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_DQMH_CLK );

                VitalPeriodPulseCheck (
                    TestSignal      =>  CLKIn,
                    TestSignalName  =>  "CLK",
                    Period          =>  tperiod_CLK,
                    PulseWidthLow   =>  tpw_CLK_negedge,
                    PulseWidthHigh  =>  tpw_CLK_posedge,
                    PeriodData      =>  PD_CLK,
                    XOn             =>  XOn,
                    MsgOn           =>  MsgOn,
                    Violation       =>  Pviol_CLK,
                    HeaderMsg       =>  InstancePath & PartID,
                    CheckEnabled    =>  CAS_Lat=2 );

                VitalPeriodPulseCheck (
                    TestSignal      =>  CLKIn,
                    TestSignalName  =>  "CLK",
                    Period          =>  tperiod_CLK1,
                    PulseWidthLow   =>  tpw_CLK_negedge,
                    PulseWidthHigh  =>  tpw_CLK_posedge,
                    PeriodData      =>  PD_CLK,
                    XOn             =>  XOn,
                    MsgOn           =>  MsgOn,
                    Violation       =>  Pviol_CLK,
                    HeaderMsg       =>  InstancePath & PartID,
                    CheckEnabled    =>  CAS_Lat/=2 );