mt48lc4m16.vhd
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VHD
1,475 行
---------------------------------------------------------------------------------- File Name: mt48lc4m16.vhd---------------------------------------------------------------------------------- Copyright (C) 2004 Free Model Foundry; http://www.FreeModelFoundry.com---- This program is free software; you can redistribute it and/or modify-- it under the terms of the GNU General Public License version 2 as-- published by the Free Software Foundation.---- MODIFICATION HISTORY:---- version: | author: | mod date: | changes made:-- V1.0 M.Marinkovic 04 Jan 15 Initial release---------------------------------------------------------------------------------- PART DESCRIPTION:---- Library: RAM-- Technology: CMOS-- Part: mt48lc4m16---- Description: 1M x 16 x 4Banks SDRAM--------------------------------------------------------------------------------LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.all; USE IEEE.VITAL_primitives.all; USE STD.textio.ALL;LIBRARY FMF; USE FMF.gen_utils.ALL; USE FMF.conversions.ALL;---------------------------------------------------------------------------------- ENTITY DECLARATION--------------------------------------------------------------------------------ENTITY mt48lc4m16 IS GENERIC ( -- tipd delays: interconnect path delays tipd_BA0 : VitalDelayType01 := VitalZeroDelay01; tipd_BA1 : VitalDelayType01 := VitalZeroDelay01; tipd_DQML : VitalDelayType01 := VitalZeroDelay01; tipd_DQMH : VitalDelayType01 := VitalZeroDelay01; tipd_DQ0 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ1 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ2 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ3 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ4 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ5 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ6 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ7 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ8 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ9 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ10 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ11 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ12 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ13 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ14 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ15 : VitalDelayType01 := VitalZeroDelay01; tipd_CLK : VitalDelayType01 := VitalZeroDelay01; tipd_CKE : VitalDelayType01 := VitalZeroDelay01; tipd_A0 : VitalDelayType01 := VitalZeroDelay01; tipd_A1 : VitalDelayType01 := VitalZeroDelay01; tipd_A2 : VitalDelayType01 := VitalZeroDelay01; tipd_A3 : VitalDelayType01 := VitalZeroDelay01; tipd_A4 : VitalDelayType01 := VitalZeroDelay01; tipd_A5 : VitalDelayType01 := VitalZeroDelay01; tipd_A6 : VitalDelayType01 := VitalZeroDelay01; tipd_A7 : VitalDelayType01 := VitalZeroDelay01; tipd_A8 : VitalDelayType01 := VitalZeroDelay01; tipd_A9 : VitalDelayType01 := VitalZeroDelay01; tipd_A10 : VitalDelayType01 := VitalZeroDelay01; tipd_A11 : VitalDelayType01 := VitalZeroDelay01; tipd_WENeg : VitalDelayType01 := VitalZeroDelay01; tipd_RASNeg : VitalDelayType01 := VitalZeroDelay01; tipd_CSNeg : VitalDelayType01 := VitalZeroDelay01; tipd_CASNeg : VitalDelayType01 := VitalZeroDelay01; -- tpd delays tAC tHZ tpd_CLK_DQ0 : VitalDelayType01Z := UnitDelay01Z; --CL2 tpd_CLK_DQ1 : VitalDelayType01Z := UnitDelay01Z; --CL3 -- tpw values: pulse widths tpw_CLK_posedge : VitalDelayType := UnitDelay; --tCH tpw_CLK_negedge : VitalDelayType := UnitDelay; --tCL -- tsetup values: setup times tsetup_A0_CLK : VitalDelayType := UnitDelay; --tAS tsetup_DQ0_CLK : VitalDelayType := UnitDelay; --tDS tsetup_CKE_CLK : VitalDelayType := UnitDelay; --tCKS tsetup_CSNeg_CLK : VitalDelayType := UnitDelay; --tCMS -- thold values: hold times thold_A0_CLK : VitalDelayType := UnitDelay; --tAH thold_DQ0_CLK : VitalDelayType := UnitDelay; --tDH thold_CKE_CLK : VitalDelayType := UnitDelay; --tCKH thold_CSNeg_CLK : VitalDelayType := UnitDelay; --tCMH -- tperiod_min: minimum clock period = 1/max freq tCK tperiod_CLK : VitalDelayType := UnitDelay; --CL2 tperiod_CLK1 : VitalDelayType := UnitDelay; --CL3 -- tdevice values: values for internal delays tdevice_REF : VitalDelayType := 15_625 ns; tdevice_TRC : VitalDelayType := 66 ns; tdevice_TRCD : VitalDelayType := 20 ns; tdevice_TRP : VitalDelayType := 20 ns; tdevice_TRFC : VitalDelayType := 66 ns; tdevice_TRAS : VitalDelayType01 := (44 ns, 120_000 ns); -- tpowerup: Power up initialization time. Data sheets say 200 us. -- May be shortened during simulation debug. tpowerup : TIME := 200 us; -- generic control parameters InstancePath : STRING := DefaultInstancePath; TimingChecksOn : BOOLEAN := DefaultTimingChecks; MsgOn : BOOLEAN := DefaultMsgOn; XOn : BOOLEAN := DefaultXon; SeverityMode : SEVERITY_LEVEL := WARNING; -- memory file to be loaded mem_file_name : STRING :="none"; --"mt48lc4m16.mem"; -- For FMF SDF technology file usage TimingModel : STRING := DefaultTimingModel ); PORT ( BA0 : IN std_logic := 'U'; BA1 : IN std_logic := 'U'; DQML : IN std_logic := 'U'; DQMH : IN std_logic := 'U'; DQ0 : INOUT std_logic := 'U'; DQ1 : INOUT std_logic := 'U'; DQ2 : INOUT std_logic := 'U'; DQ3 : INOUT std_logic := 'U'; DQ4 : INOUT std_logic := 'U'; DQ5 : INOUT std_logic := 'U'; DQ6 : INOUT std_logic := 'U'; DQ7 : INOUT std_logic := 'U'; DQ8 : INOUT std_logic := 'U'; DQ9 : INOUT std_logic := 'U'; DQ10 : INOUT std_logic := 'U'; DQ11 : INOUT std_logic := 'U'; DQ12 : INOUT std_logic := 'U'; DQ13 : INOUT std_logic := 'U'; DQ14 : INOUT std_logic := 'U'; DQ15 : INOUT std_logic := 'U'; CLK : IN std_logic := 'U'; CKE : IN std_logic := 'U'; A0 : IN std_logic := 'U'; A1 : IN std_logic := 'U'; A2 : IN std_logic := 'U'; A3 : IN std_logic := 'U'; A4 : IN std_logic := 'U'; A5 : IN std_logic := 'U'; A6 : IN std_logic := 'U'; A7 : IN std_logic := 'U'; A8 : IN std_logic := 'U'; A9 : IN std_logic := 'U'; A10 : IN std_logic := 'U'; A11 : IN std_logic := 'U'; WENeg : IN std_logic := 'U'; RASNeg : IN std_logic := 'U'; CSNeg : IN std_logic := 'U'; CASNeg : IN std_logic := 'U' ); ATTRIBUTE VITAL_LEVEL0 of mt48lc4m16 : ENTITY IS TRUE;END mt48lc4m16;---------------------------------------------------------------------------------- ARCHITECTURE DECLARATION--------------------------------------------------------------------------------ARCHITECTURE vhdl_behavioral of mt48lc4m16 IS ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE; CONSTANT partID : STRING := "mt48lc4m16"; CONSTANT hi_bank : NATURAL := 3; CONSTANT HiAddrBit : NATURAL := 11; CONSTANT HiColBit : NATURAL := 7; CONSTANT HiDataBit : NATURAL := 15; CONSTANT depth : NATURAL := 16#FFFFF#; --Bank depth SIGNAL CKEreg : X01 := 'X'; SIGNAL PoweredUp : boolean := false; SIGNAL DQML_ipd : std_ulogic := 'U'; SIGNAL DQMH_ipd : std_ulogic := 'U'; SIGNAL DQ0_ipd : std_ulogic := 'U'; SIGNAL DQ1_ipd : std_ulogic := 'U'; SIGNAL DQ2_ipd : std_ulogic := 'U'; SIGNAL DQ3_ipd : std_ulogic := 'U'; SIGNAL DQ4_ipd : std_ulogic := 'U'; SIGNAL DQ5_ipd : std_ulogic := 'U'; SIGNAL DQ6_ipd : std_ulogic := 'U'; SIGNAL DQ7_ipd : std_ulogic := 'U'; SIGNAL DQ8_ipd : std_ulogic := 'U'; SIGNAL DQ9_ipd : std_ulogic := 'U'; SIGNAL DQ10_ipd : std_ulogic := 'U'; SIGNAL DQ11_ipd : std_ulogic := 'U'; SIGNAL DQ12_ipd : std_ulogic := 'U'; SIGNAL DQ13_ipd : std_ulogic := 'U'; SIGNAL DQ14_ipd : std_ulogic := 'U'; SIGNAL DQ15_ipd : std_ulogic := 'U'; SIGNAL BA0_ipd : std_ulogic := 'U'; SIGNAL BA1_ipd : std_ulogic := 'U'; SIGNAL CLK_ipd : std_ulogic := 'U'; SIGNAL CKE_ipd : std_ulogic := 'U'; SIGNAL A0_ipd : std_ulogic := 'U'; SIGNAL A1_ipd : std_ulogic := 'U'; SIGNAL A2_ipd : std_ulogic := 'U'; SIGNAL A3_ipd : std_ulogic := 'U'; SIGNAL A4_ipd : std_ulogic := 'U'; SIGNAL A5_ipd : std_ulogic := 'U'; SIGNAL A6_ipd : std_ulogic := 'U'; SIGNAL A7_ipd : std_ulogic := 'U'; SIGNAL A8_ipd : std_ulogic := 'U'; SIGNAL A9_ipd : std_ulogic := 'U'; SIGNAL A10_ipd : std_ulogic := 'U'; SIGNAL A11_ipd : std_ulogic := 'U'; SIGNAL WENeg_ipd : std_ulogic := 'U'; SIGNAL RASNeg_ipd : std_ulogic := 'U'; SIGNAL CSNeg_ipd : std_ulogic := 'U'; SIGNAL CASNeg_ipd : std_ulogic := 'U'; SIGNAL DQML_nwv : UX01 := 'U'; SIGNAL DQMH_nwv : UX01 := 'U'; SIGNAL DQ0_nwv : UX01 := 'U'; SIGNAL DQ1_nwv : UX01 := 'U'; SIGNAL DQ2_nwv : UX01 := 'U'; SIGNAL DQ3_nwv : UX01 := 'U'; SIGNAL DQ4_nwv : UX01 := 'U'; SIGNAL DQ5_nwv : UX01 := 'U'; SIGNAL DQ6_nwv : UX01 := 'U'; SIGNAL DQ7_nwv : UX01 := 'U'; SIGNAL DQ8_nwv : UX01 := 'U'; SIGNAL DQ9_nwv : UX01 := 'U'; SIGNAL DQ10_nwv : UX01 := 'U'; SIGNAL DQ11_nwv : UX01 := 'U'; SIGNAL DQ12_nwv : UX01 := 'U'; SIGNAL DQ13_nwv : UX01 := 'U'; SIGNAL DQ14_nwv : UX01 := 'U'; SIGNAL DQ15_nwv : UX01 := 'U'; SIGNAL BA0_nwv : UX01 := 'U'; SIGNAL BA1_nwv : UX01 := 'U'; SIGNAL A0_nwv : UX01 := 'U'; SIGNAL A1_nwv : UX01 := 'U'; SIGNAL A2_nwv : UX01 := 'U'; SIGNAL A3_nwv : UX01 := 'U'; SIGNAL A4_nwv : UX01 := 'U'; SIGNAL A5_nwv : UX01 := 'U'; SIGNAL A6_nwv : UX01 := 'U'; SIGNAL A7_nwv : UX01 := 'U'; SIGNAL A8_nwv : UX01 := 'U'; SIGNAL A9_nwv : UX01 := 'U'; SIGNAL A10_nwv : UX01 := 'U'; SIGNAL A11_nwv : UX01 := 'U'; SIGNAL CLK_nwv : std_ulogic := 'U'; SIGNAL CKE_nwv : std_ulogic := 'U'; SIGNAL WENeg_nwv : std_ulogic := 'U'; SIGNAL RASNeg_nwv : std_ulogic := 'U'; SIGNAL CSNeg_nwv : std_ulogic := 'U'; SIGNAL CASNeg_nwv : std_ulogic := 'U'; SIGNAL rct_in : std_ulogic := '0'; SIGNAL rct_out : std_ulogic := '0'; SIGNAL rcdt_in : std_ulogic_vector(3 downto 0) := (others => '0'); SIGNAL rcdt_out : std_ulogic_vector(3 downto 0) := (others => '0'); SIGNAL pre_in : std_ulogic := '0'; SIGNAL pre_out : std_ulogic := '0'; SIGNAL refreshed_in : std_ulogic := '0'; SIGNAL refreshed_out : std_ulogic := '0'; SIGNAL rfc_out : std_ulogic := '0'; SIGNAL rfc_in : std_ulogic := '0'; SIGNAL ras_in : std_ulogic_vector(3 downto 0) := (others => '0'); SIGNAL ras_out : std_ulogic_vector(3 downto 0) := (others => '0');BEGIN ---------------------------------------------------------------------------- -- Internal Delays ---------------------------------------------------------------------------- -- Artificial VITAL primitives to incorporate internal delays REF : VitalBuf (refreshed_out, refreshed_in, (UnitDelay, tdevice_REF)); TRC : VitalBuf (rct_out, rct_in, (tdevice_TRC, VitalZeroDelay)); TRCD : VitalBuf (rcdt_out(0), rcdt_in(0), (VitalZeroDelay, tdevice_TRCD)); TRCD1 : VitalBuf (rcdt_out(1), rcdt_in(1), (VitalZeroDelay, tdevice_TRCD)); TRCD2 : VitalBuf (rcdt_out(2), rcdt_in(2), (VitalZeroDelay, tdevice_TRCD)); TRCD3 : VitalBuf (rcdt_out(3), rcdt_in(3), (VitalZeroDelay, tdevice_TRCD)); TRP : VitalBuf (pre_out, pre_in, (tdevice_TRP, UnitDelay)); TRFC : VitalBuf (rfc_out, rfc_in, (tdevice_TRFC, UnitDelay)); TRAS : VitalBuf (ras_out(0), ras_in(0), tdevice_TRAS); TRAS1 : VitalBuf (ras_out(1), ras_in(1), tdevice_TRAS); TRAS2 : VitalBuf (ras_out(2), ras_in(2), tdevice_TRAS); TRAS3 : VitalBuf (ras_out(3), ras_in(3), tdevice_TRAS); ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1 : VitalWireDelay (DQML_ipd, DQML, tipd_DQML); w_2 : VitalWireDelay (DQMH_ipd, DQMH, tipd_DQMH); w_3 : VitalWireDelay (DQ0_ipd, DQ0, tipd_DQ0); w_4 : VitalWireDelay (DQ1_ipd, DQ1, tipd_DQ1); w_5 : VitalWireDelay (DQ2_ipd, DQ2, tipd_DQ2); w_6 : VitalWireDelay (DQ3_ipd, DQ3, tipd_DQ3); w_7 : VitalWireDelay (DQ4_ipd, DQ4, tipd_DQ4);⌨️ 快捷键说明
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