idt70t3519.vhd

来自「VHDL的ram和fifo model code 包含众多的厂家」· VHDL 代码 · 共 1,305 行 · 第 1/5 页

-------------------------------------------------------------------------------
    TimingCheckP: PROCESS(AddressL, DataInL, RWL, CEL, OEL, ClockL, PLNegL,
                          ADSNegL, CNTENNegL, REPEATNegL, BENegL,
                          AddressR, DataInR, RWR, CER, OER, ClockR, PLNegR,
                          ADSNegR, CNTENNegR, REPEATNegR, BENegR,
                          TDI, TCK, TMS, TRSTNeg)

        TYPE tap_state_type IS (Test_Logic_Reset,
                                Run_Test_Idle,
                                Select_DR_Scan,
                                Capture_DR,
                                Shift_DR,
                                Exit1_DR,
                                Pause_DR,
                                Exit2_DR,
                                Update_DR,
                                Select_IR_Scan,
                                Capture_IR,
                                Shift_IR,
                                Exit1_IR,
                                Pause_IR,
                                Exit2_IR,
                                Update_IR
                                );

        VARIABLE TAP_state   : tap_state_type;

        VARIABLE BYReg       : std_logic := '0';
        VARIABLE MSReg       : std_logic_vector(1 downto 0) := "00";
        VARIABLE IReg        : std_logic_vector(3 downto 0);
        VARIABLE MRReg       : std_logic_vector(25 downto 0)
                                    := (others => '0');
        VARIABLE IDReg       : std_logic_vector(31 downto 0);
        VARIABLE BYTmp       : std_logic;
        VARIABLE MSTmp       : std_logic_vector(1 downto 0);
        VARIABLE ITmp        : std_logic_vector(3 downto 0);
        VARIABLE MRTmp       : std_logic_vector(25 downto 0);
        VARIABLE IDTmp       : std_logic_vector(31 downto 0);
        VARIABLE BSTmp       : std_logic_vector(149 downto 0)
                                    := (others => '1');
        VARIABLE TDOTmp      : std_logic;

        VARIABLE Shift       : BOOLEAN := false;
        VARIABLE UpdateIR    : BOOLEAN := false;
        VARIABLE UpdateDR    : BOOLEAN := false;

        -- Output Glitch Detection Variables
        VARIABLE TDO_GlitchData         : VitalGlitchDataType;

        VARIABLE TDO_zd                 : std_logic := 'Z';

        VARIABLE Tviol_A0_CENeg   : X01 := '0';
        VARIABLE TD_A0_CENeg      : VitalTimingDataType;

        VARIABLE Pviol_OENeg      : X01 := '0';
        VARIABLE PD_OENeg         : VitalPeriodDataType :=
                                                   VitalPeriodDataInit;

        VARIABLE Violation        : X01 := '0';

        VARIABLE TD_AL_CLK          : VitalTimingDataType;
        VARIABLE Tviol_AL_CLK       : X01 := '0';
        VARIABLE TD_AR_CLK          : VitalTimingDataType;
        VARIABLE Tviol_AR_CLK       : X01 := '0';
        VARIABLE TD_DL_CLK          : VitalTimingDataType;
        VARIABLE Tviol_DL_CLK       : X01 := '0';
        VARIABLE TD_DR_CLK          : VitalTimingDataType;
        VARIABLE Tviol_DR_CLK       : X01 := '0';
        VARIABLE TD_CEL_CLK         : VitalTimingDataType;
        VARIABLE Tviol_CEL_CLK      : X01 := '0';
        VARIABLE TD_CER_CLK         : VitalTimingDataType;
        VARIABLE Tviol_CER_CLK      : X01 := '0';
        VARIABLE TD_BEL_CLK         : VitalTimingDataType;
        VARIABLE Tviol_BEL_CLK      : X01 := '0';
        VARIABLE TD_BER_CLK         : VitalTimingDataType;
        VARIABLE Tviol_BER_CLK      : X01 := '0';
        VARIABLE TD_RWL_CLK         : VitalTimingDataType;
        VARIABLE Tviol_RWL_CLK      : X01 := '0';
        VARIABLE TD_RWR_CLK         : VitalTimingDataType;
        VARIABLE Tviol_RWR_CLK      : X01 := '0';
        VARIABLE TD_ADSL_CLK        : VitalTimingDataType;
        VARIABLE Tviol_ADSL_CLK     : X01 := '0';
        VARIABLE TD_ADSR_CLK        : VitalTimingDataType;
        VARIABLE Tviol_ADSR_CLK     : X01 := '0';
        VARIABLE TD_CNTL_CLK        : VitalTimingDataType;
        VARIABLE Tviol_CNTL_CLK     : X01 := '0';
        VARIABLE TD_CNTR_CLK        : VitalTimingDataType;
        VARIABLE Tviol_CNTR_CLK     : X01 := '0';
        VARIABLE TD_RPTL_CLK        : VitalTimingDataType;
        VARIABLE Tviol_RPTL_CLK     : X01 := '0';
        VARIABLE TD_RPTR_CLK        : VitalTimingDataType;
        VARIABLE Tviol_RPTR_CLK     : X01 := '0';
        VARIABLE TD_TDI_TCK         : VitalTimingDataType;
        VARIABLE Tviol_TDI_TCK      : X01 := '0';
        VARIABLE PD_CLKP            : VitalPeriodDataType :=
                                                   VitalPeriodDataInit;
        VARIABLE Pviol_CLKP         : X01 := '0';
        VARIABLE PD_CLKF            : VitalPeriodDataType :=
                                                   VitalPeriodDataInit;
        VARIABLE Pviol_CLKF         : X01 := '0';
        VARIABLE PD_CLKP1           : VitalPeriodDataType :=
                                                   VitalPeriodDataInit;
        VARIABLE Pviol_CLKP1        : X01 := '0';
        VARIABLE PD_CLKF1           : VitalPeriodDataType :=
                                                   VitalPeriodDataInit;
        VARIABLE Pviol_CLKF1        : X01 := '0';
        VARIABLE PD_TCK             : VitalPeriodDataType :=
                                                   VitalPeriodDataInit;
        VARIABLE Pviol_TCK          : X01 := '0';
        VARIABLE PD_TRST            : VitalPeriodDataType :=
                                                   VitalPeriodDataInit;
        VARIABLE Pviol_TRST         : X01 := '0';

    BEGIN
        IF TimingChecksOn THEN

            VitalSetupHoldCheck (
                TestSignal      => AddressL,
                TestSignalName  => "Left Address",
                RefSignal       => ClockL,
                RefSignalName   => "ClockL",
                SetupHigh       => tsetup_A0_CLK,
                SetupLow        => tsetup_A0_CLK,
                HoldHigh        => thold_A0_CLK,
                HoldLow         => thold_A0_CLK,
                CheckEnabled    => true,
                RefTransition   => '/',
                HeaderMsg       => InstancePath & PartID,
                TimingData      => TD_AL_CLK,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_AL_CLK );

            VitalSetupHoldCheck (
                TestSignal      => AddressR,
                TestSignalName  => "Right Address",
                RefSignal       => ClockR,
                RefSignalName   => "ClockR",
                SetupHigh       => tsetup_A0_CLK,
                SetupLow        => tsetup_A0_CLK,
                HoldHigh        => thold_A0_CLK,
                HoldLow         => thold_A0_CLK,
                CheckEnabled    => true,
                RefTransition   => '/',
                HeaderMsg       => InstancePath & PartID,
                TimingData      => TD_AR_CLK,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_AR_CLK );

            VitalSetupHoldCheck (
                TestSignal      => DataInL,
                TestSignalName  => "Left Data",
                RefSignal       => ClockL,
                RefSignalName   => "ClockL",
                SetupHigh       => tsetup_A0_CLK,
                SetupLow        => tsetup_A0_CLK,
                HoldHigh        => thold_A0_CLK,
                HoldLow         => thold_A0_CLK,
                CheckEnabled    => true,
                RefTransition   => '/',
                HeaderMsg       => InstancePath & PartID,
                TimingData      => TD_DL_CLK,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_DL_CLK );

            VitalSetupHoldCheck (
                TestSignal      => DataInR,
                TestSignalName  => "Right Data",
                RefSignal       => ClockR,
                RefSignalName   => "ClockR",
                SetupHigh       => tsetup_A0_CLK,
                SetupLow        => tsetup_A0_CLK,
                HoldHigh        => thold_A0_CLK,
                HoldLow         => thold_A0_CLK,
                CheckEnabled    => true,
                RefTransition   => '/',
                HeaderMsg       => InstancePath & PartID,
                TimingData      => TD_DR_CLK,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_DR_CLK );

            VitalSetupHoldCheck (
                TestSignal      => CEL,
                TestSignalName  => "CE Left",
                RefSignal       => ClockL,
                RefSignalName   => "ClockL",
                SetupHigh       => tsetup_A0_CLK,
                SetupLow        => tsetup_A0_CLK,
                HoldHigh        => thold_A0_CLK,
                HoldLow         => thold_A0_CLK,
                CheckEnabled    => true,
                RefTransition   => '/',
                HeaderMsg       => InstancePath & PartID,
                TimingData      => TD_CEL_CLK,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_CEL_CLK );

            VitalSetupHoldCheck (
                TestSignal      => CER,
                TestSignalName  => "CE Right",
                RefSignal       => ClockR,
                RefSignalName   => "ClockR",
                SetupHigh       => tsetup_A0_CLK,
                SetupLow        => tsetup_A0_CLK,
                HoldHigh        => thold_A0_CLK,
                HoldLow         => thold_A0_CLK,
                CheckEnabled    => true,
                RefTransition   => '/',
                HeaderMsg       => InstancePath & PartID,
                TimingData      => TD_CER_CLK,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_CER_CLK );

            VitalSetupHoldCheck (
                TestSignal      => BENegL,
                TestSignalName  => "BE Left",
                RefSignal       => ClockL,
                RefSignalName   => "ClockL",
                SetupHigh       => tsetup_A0_CLK,
                SetupLow        => tsetup_A0_CLK,
                HoldHigh        => thold_A0_CLK,
                HoldLow         => thold_A0_CLK,
                CheckEnabled    => true,
                RefTransition   => '/',
                HeaderMsg       => InstancePath & PartID,
                TimingData      => TD_BEL_CLK,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_BEL_CLK );

            VitalSetupHoldCheck (
                TestSignal      => BENegR,
                TestSignalName  => "BE Right",
                RefSignal       => ClockR,
                RefSignalName   => "ClockR",
                SetupHigh       => tsetup_A0_CLK,
                SetupLow        => tsetup_A0_CLK,
                HoldHigh        => thold_A0_CLK,
                HoldLow         => thold_A0_CLK,
                CheckEnabled    => true,
                RefTransition   => '/',
                HeaderMsg       => InstancePath & PartID,
                TimingData      => TD_BER_CLK,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_BER_CLK );

            VitalSetupHoldCheck (
                TestSignal      => RWL,
                TestSignalName  => "R/W Left",
                RefSignal       => ClockL,
                RefSignalName   => "ClockL",
                SetupHigh       => tsetup_A0_CLK,
                SetupLow        => tsetup_A0_CLK,
                HoldHigh        => thold_A0_CLK,
                HoldLo