idt70t3589dr.vhd

来自「VHDL的ram和fifo model code 包含众多的厂家」· VHDL 代码 · 共 1,309 行 · 第 1/5 页

                TestSignalName  => "Right Address",
                RefSignal       => ClockR,
                RefSignalName   => "ClockR",
                SetupHigh       => tsetup_A0_CLK,
                SetupLow        => tsetup_A0_CLK,
                HoldHigh        => thold_A0_CLK,
                HoldLow         => thold_A0_CLK,
                CheckEnabled    => true,
                RefTransition   => '/',
                HeaderMsg       => InstancePath & PartID,
                TimingData      => TD_AR_CLK,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_AR_CLK );

            VitalSetupHoldCheck (
                TestSignal      => DataInL,
                TestSignalName  => "Left Data",
                RefSignal       => ClockL,
                RefSignalName   => "ClockL",
                SetupHigh       => tsetup_A0_CLK,
                SetupLow        => tsetup_A0_CLK,
                HoldHigh        => thold_A0_CLK,
                HoldLow         => thold_A0_CLK,
                CheckEnabled    => true,
                RefTransition   => '/',
                HeaderMsg       => InstancePath & PartID,
                TimingData      => TD_DL_CLK,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_DL_CLK );

            VitalSetupHoldCheck (
                TestSignal      => DataInR,
                TestSignalName  => "Right Data",
                RefSignal       => ClockR,
                RefSignalName   => "ClockR",
                SetupHigh       => tsetup_A0_CLK,
                SetupLow        => tsetup_A0_CLK,
                HoldHigh        => thold_A0_CLK,
                HoldLow         => thold_A0_CLK,
                CheckEnabled    => true,
                RefTransition   => '/',
                HeaderMsg       => InstancePath & PartID,
                TimingData      => TD_DR_CLK,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_DR_CLK );

            VitalSetupHoldCheck (
                TestSignal      => CEL,
                TestSignalName  => "CE Left",
                RefSignal       => ClockL,
                RefSignalName   => "ClockL",
                SetupHigh       => tsetup_A0_CLK,
                SetupLow        => tsetup_A0_CLK,
                HoldHigh        => thold_A0_CLK,
                HoldLow         => thold_A0_CLK,
                CheckEnabled    => true,
                RefTransition   => '/',
                HeaderMsg       => InstancePath & PartID,
                TimingData      => TD_CEL_CLK,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_CEL_CLK );

            VitalSetupHoldCheck (
                TestSignal      => CER,
                TestSignalName  => "CE Right",
                RefSignal       => ClockR,
                RefSignalName   => "ClockR",
                SetupHigh       => tsetup_A0_CLK,
                SetupLow        => tsetup_A0_CLK,
                HoldHigh        => thold_A0_CLK,
                HoldLow         => thold_A0_CLK,
                CheckEnabled    => true,
                RefTransition   => '/',
                HeaderMsg       => InstancePath & PartID,
                TimingData      => TD_CER_CLK,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_CER_CLK );

            VitalSetupHoldCheck (
                TestSignal      => BENegL,
                TestSignalName  => "BE Left",
                RefSignal       => ClockL,
                RefSignalName   => "ClockL",
                SetupHigh       => tsetup_A0_CLK,
                SetupLow        => tsetup_A0_CLK,
                HoldHigh        => thold_A0_CLK,
                HoldLow         => thold_A0_CLK,
                CheckEnabled    => true,
                RefTransition   => '/',
                HeaderMsg       => InstancePath & PartID,
                TimingData      => TD_BEL_CLK,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_BEL_CLK );

            VitalSetupHoldCheck (
                TestSignal      => BENegR,
                TestSignalName  => "BE Right",
                RefSignal       => ClockR,
                RefSignalName   => "ClockR",
                SetupHigh       => tsetup_A0_CLK,
                SetupLow        => tsetup_A0_CLK,
                HoldHigh        => thold_A0_CLK,
                HoldLow         => thold_A0_CLK,
                CheckEnabled    => true,
                RefTransition   => '/',
                HeaderMsg       => InstancePath & PartID,
                TimingData      => TD_BER_CLK,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_BER_CLK );

            VitalSetupHoldCheck (
                TestSignal      => RWL,
                TestSignalName  => "R/W Left",
                RefSignal       => ClockL,
                RefSignalName   => "ClockL",
                SetupHigh       => tsetup_A0_CLK,
                SetupLow        => tsetup_A0_CLK,
                HoldHigh        => thold_A0_CLK,
                HoldLow         => thold_A0_CLK,
                CheckEnabled    => true,
                RefTransition   => '/',
                HeaderMsg       => InstancePath & PartID,
                TimingData      => TD_RWL_CLK,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_RWL_CLK );

            VitalSetupHoldCheck (
                TestSignal      => RWR,
                TestSignalName  => "R/W Right",
                RefSignal       => ClockR,
                RefSignalName   => "ClockR",
                SetupHigh       => tsetup_A0_CLK,
                SetupLow        => tsetup_A0_CLK,
                HoldHigh        => thold_A0_CLK,
                HoldLow         => thold_A0_CLK,
                CheckEnabled    => true,
                RefTransition   => '/',
                HeaderMsg       => InstancePath & PartID,
                TimingData      => TD_RWR_CLK,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_RWR_CLK );

            VitalSetupHoldCheck (
                TestSignal      => ADSNegL,
                TestSignalName  => "ADS Left",
                RefSignal       => ClockL,
                RefSignalName   => "ClockL",
                SetupHigh       => tsetup_A0_CLK,
                SetupLow        => tsetup_A0_CLK,
                HoldHigh        => thold_A0_CLK,
                HoldLow         => thold_A0_CLK,
                CheckEnabled    => true,
                RefTransition   => '/',
                HeaderMsg       => InstancePath & PartID,
                TimingData      => TD_ADSL_CLK,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_ADSL_CLK );

            VitalSetupHoldCheck (
                TestSignal      => ADSNegR,
                TestSignalName  => "ADS Right",
                RefSignal       => ClockR,
                RefSignalName   => "ClockR",
                SetupHigh       => tsetup_A0_CLK,
                SetupLow        => tsetup_A0_CLK,
                HoldHigh        => thold_A0_CLK,
                HoldLow         => thold_A0_CLK,
                CheckEnabled    => true,
                RefTransition   => '/',
                HeaderMsg       => InstancePath & PartID,
                TimingData      => TD_ADSR_CLK,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_ADSR_CLK );

            VitalSetupHoldCheck (
                TestSignal      => CNTENNegL,
                TestSignalName  => "CntEn Left",
                RefSignal       => ClockL,
                RefSignalName   => "ClockL",
                SetupHigh       => tsetup_A0_CLK,
                SetupLow        => tsetup_A0_CLK,
                HoldHigh        => thold_A0_CLK,
                HoldLow         => thold_A0_CLK,
                CheckEnabled    => true,
                RefTransition   => '/',
                HeaderMsg       => InstancePath & PartID,
                TimingData      => TD_CNTL_CLK,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_CNTL_CLK );

            VitalSetupHoldCheck (
                TestSignal      => CNTENNegR,
                TestSignalName  => "CntEn Right",
                RefSignal       => ClockR,
                RefSignalName   => "ClockR",
                SetupHigh       => tsetup_A0_CLK,
                SetupLow        => tsetup_A0_CLK,
                HoldHigh        => thold_A0_CLK,
                HoldLow         => thold_A0_CLK,
                CheckEnabled    => true,
                RefTransition   => '/',
                HeaderMsg       => InstancePath & PartID,
                TimingData      => TD_CNTR_CLK,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_CNTR_CLK );

            VitalSetupHoldCheck (
                TestSignal      => REPEATNegL,
                TestSignalName  => "REPEAT Left",
                RefSignal       => ClockL,
                RefSignalName   => "ClockL",
                SetupHigh       => tsetup_A0_CLK,
                SetupLow        => tsetup_A0_CLK,
                HoldHigh        => thold_A0_CLK,
                HoldLow         => thold_A0_CLK,
                CheckEnabled    => true,
                RefTransition   => '/',
                HeaderMsg       => InstancePath & PartID,
                TimingData      => TD_RPTL_CLK,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_RPTL_CLK );

            VitalSetupHoldCheck (
                TestSignal      => REPEATNegR,
                TestSignalName  => "REPEAT Right",
                RefSignal       => ClockR,
                RefSignalName   => "ClockR",
                SetupHigh       => tsetup_A0_CLK,
                SetupLow        => tsetup_A0_CLK,
                HoldHigh        => thold_A0_CLK,
                HoldLow         => thold_A0_CLK,
                CheckEnabled    => true,
                RefTransition   => '/',
                HeaderMsg       => InstancePath & PartID,
                TimingData      => TD_RPTR_CLK,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_RPTR_CLK );

            VitalPeriodPulseCheck (
                TestSignal      =>  ClockL,
                TestSignalName  =>  "Left Clock",
                Period          =>  tperiod_CLKP,
                PulseWidthLow   =>  tpw_CLKP_negedge,
                PulseWidthHigh  =>  tpw_CLKP_posedge,
                PeriodData      =>  PD_CLKP,
                X