idt72821.vhd

VHDL的ram和fifo model code 包含众多的厂家

                                 RCLK, REN1Neg, REN2Neg, OENeg )
            -- Timing Check Variable

            -- Pulse Width and Period Check Variables

            VARIABLE Pviol_WCLK      : X01 := '0';
            VARIABLE PD_WCLK         : VitalPeriodDataType :=
                                       VitalPeriodDataInit;

            VARIABLE Pviol_RCLK      : X01 := '0';
            VARIABLE PD_RCLK         : VitalPeriodDataType :=
                                       VitalPeriodDataInit;

            VARIABLE Pviol_RSNeg     : X01 := '0';
            VARIABLE PD_RSNeg        : VitalPeriodDataType :=
                                       VitalPeriodDataInit;

            -- Setup/Hold Check Variables

            VARIABLE Tviol_D0_WCLK       : X01 := '0';
            VARIABLE TD_D0_WCLK          : VitalTimingDataType;

            VARIABLE Tviol_REN1Neg_RCLK       : X01 := '0';
            VARIABLE TD_REN1Neg_RCLK          : VitalTimingDataType;

            VARIABLE Tviol_REN2Neg_RCLK  : X01 := '0';
            VARIABLE TD_REN2Neg_RCLK     : VitalTimingDataType;

            VARIABLE Tviol_WEN1Neg_WCLK       : X01 := '0';
            VARIABLE TD_WEN1Neg_WCLK          : VitalTimingDataType;

            VARIABLE Tviol_WEN2LDNeg_WCLK  : X01 := '0';
            VARIABLE TD_WEN2LDNeg_WCLK     : VitalTimingDataType;

            VARIABLE Tviol_REN1Neg_RSNeg : X01 := '0';
            VARIABLE TD_REN1Neg_RSNeg    : VitalTimingDataType;

            VARIABLE Tviol_REN2Neg_RSNeg : X01 := '0';
            VARIABLE TD_REN2Neg_RSNeg    : VitalTimingDataType;

            VARIABLE Tviol_WEN1Neg_RSNeg : X01 := '0';
            VARIABLE TD_WEN1Neg_RSNeg    : VitalTimingDataType;

            VARIABLE Tviol_WEN2LDNeg_RSNeg : X01 := '0';
            VARIABLE TD_WEN2LDNeg_RSNeg    : VitalTimingDataType;

            -- Recovery Check Variables

            VARIABLE Rviol_REN1Neg_RSNeg     : X01 := '0';
            VARIABLE RD_REN1Neg_RSNeg        : VitalTimingDataType;

            VARIABLE Rviol_REN2Neg_RSNeg     : X01 := '0';
            VARIABLE RD_REN2Neg_RSNeg        : VitalTimingDataType;

            VARIABLE Rviol_WEN1Neg_RSNeg     : X01 := '0';
            VARIABLE RD_WEN1Neg_RSNeg        : VitalTimingDataType;

            VARIABLE Rviol_WEN2LDNeg_RSNeg     : X01 := '0';
            VARIABLE RD_WEN2LDNeg_RSNeg        : VitalTimingDataType;

            -- Violation variable (used to OR all individual violatiions)

            VARIABLE Violation               : X01 := '0';

          BEGIN  -- timing check process

            IF (TimingChecksON) THEN

              Pviol_WCLK            := '0';
              Pviol_RCLK            := '0';
              Pviol_RSNeg           := '0';
              Tviol_D0_WCLK         := '0';
              Tviol_REN1Neg_RCLK    := '0';
              Tviol_REN2Neg_RCLK    := '0';
              Tviol_WEN1Neg_WCLK    := '0';
              Tviol_WEN2LDNeg_WCLK  := '0';
              Tviol_REN1Neg_RSNeg   := '0';
              Tviol_REN2Neg_RSNeg   := '0';
              Tviol_WEN1Neg_RSNeg   := '0';
              Tviol_WEN2LDNeg_RSNeg := '0';
              Rviol_REN1Neg_RSNeg   := '0';
              Rviol_REN2Neg_RSNeg   := '0';
              Rviol_WEN1Neg_RSNeg   := '0';
              Rviol_WEN2LDNeg_RSNeg := '0';

              --1. WCLK pulse ( low&high ) width and period check
              -- ( tCLK, tCLKL, tCLKH )
              IF WCLK'Event THEN
              VitalPeriodPulseCheck (
                TestSignal      => WCLK,
                TestSignalName  => "WCLK",
                Period          => tperiod_WCLK_posedge,
                PulseWidthHigh  => tpw_RCLK_posedge,
                PulseWidthLow   => tpw_RCLK_negedge,
                CheckEnabled    => TRUE,
                HeaderMsg       => InstancePath & partID,
                PeriodData      => PD_WCLK,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Pviol_WCLK);
              END IF;

        --2. RCLK pulse ( low&high ) width and period check
              -- ( tCLK, tCLKL, tCLKH )
              IF RCLK'Event THEN
              VitalPeriodPulseCheck (
                TestSignal      => RCLK,
                TestSignalName  => "RCLK",
                Period          => tperiod_RCLK_posedge,
                PulseWidthHigh  => tpw_RCLK_posedge,
                PulseWidthLow   => tpw_RCLK_negedge,
                CheckEnabled    => TRUE,
                HeaderMsg       => InstancePath & partID,
                PeriodData      => PD_RCLK,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Pviol_RCLK);
              END IF;

              --3. RSNeg pulse low width check (tRS)
              IF RSNeg'Event THEN
              VitalPeriodPulseCheck (
                TestSignal      => RSNeg,
                TestSignalName  => "RSNeg",
                PulseWidthLow   => tpw_RSNeg_negedge,
                CheckEnabled    => TRUE,
                HeaderMsg       => InstancePath & partID,
                PeriodData      => PD_RSNeg,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Pviol_RSNeg);
              END IF;

              --4. D/WCLK setup/hold time check (tDS, tDH)
              IF D'Event AND WCLK'Event THEN
              VitalSetupHoldCheck (
                TestSignal      => D,
                TestSignalName  => "D",
                RefSignal       => WCLK,
                RefSignalName   => "WCLK",
                SetupHigh       => tSetup_D0_WCLK_noedge_posedge,
                SetupLow        => tSetup_D0_WCLK_noedge_posedge,
                HoldHigh        => tHold_D0_WCLK_noedge_posedge,
                HoldLow         => tHold_D0_WCLK_noedge_posedge,
                CheckEnabled    => TRUE,
                RefTransition    => '/',
                HeaderMsg       => InstancePath & partID,
                TimingData      => TD_D0_WCLK,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_D0_WCLK);
              END IF;

              --5. WEN1Neg/WCLK setup/hold time check (tENS, tENH)
              IF WEN1Neg'Event AND WCLK'Event THEN
              VitalSetupHoldCheck (
                TestSignal      => WEN1Neg,
                TestSignalName  => "WEN1Neg",
                RefSignal       => WCLK,
                RefSignalName   => "WCLK",
                SetupLow        => tSetup_REN1Neg_RCLK_noedge_posedge,
                HoldLow         => tHold_REN1Neg_RCLK_noedge_posedge,
                CheckEnabled    => TRUE,
                RefTransition    => '/',
                HeaderMsg       => InstancePath & partID,
                TimingData      => TD_WEN1Neg_WCLK,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_WEN1Neg_WCLK);
              END IF;

              --6. WEN2LDNeg/WCLK setup/hold time check (tENS, tENH)
              IF WEN2LDNeg'Event AND WCLK'Event THEN
              VitalSetupHoldCheck (
                TestSignal      => WEN2LDNeg,
                TestSignalName  => "WEN2LDNeg",
                RefSignal       => WCLK,
                RefSignalName   => "WCLK",
                SetupHigh       => tSetup_REN1Neg_RCLK_noedge_posedge,
                SetupLow        => tSetup_REN1Neg_RCLK_noedge_posedge,
                HoldHigh        => tHold_REN1Neg_RCLK_noedge_posedge,
                HoldLow         => tHold_REN1Neg_RCLK_noedge_posedge,
                CheckEnabled    => TRUE,
                RefTransition    => '/',
                HeaderMsg       => InstancePath & partID,
                TimingData      => TD_WEN2LDNeg_WCLK,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_WEN2LDNeg_WCLK);
              END IF;

              --7. REN1Neg/RCLK setup/hold time check (tENS, tENH)
              IF REN1Neg'Event AND RCLK'Event THEN
              VitalSetupHoldCheck (
                TestSignal      => REN1Neg,
                TestSignalName  => "REN1Neg",
                RefSignal       => RCLK,
                RefSignalName   => "RCLK",
                SetupLow        => tSetup_REN1Neg_RCLK_noedge_posedge,
                HoldLow         => tHold_REN1Neg_RCLK_noedge_posedge,
                CheckEnabled    => TRUE,
                RefTransition    => '/',
                HeaderMsg       => InstancePath & partID,
                TimingData      => TD_REN1Neg_RCLK,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_REN1Neg_RCLK);
              END IF;

              --8. REN2Neg/RCLK setup/hold time check (tENS, tENH)
              IF REN2Neg'Event AND RCLK'Event THEN
              VitalSetupHoldCheck (
                TestSignal      => REN2Neg,
                TestSignalName  => "REN2Neg",
                RefSignal       => RCLK,
                RefSignalName   => "RCLK",
                SetupLow        => tSetup_REN1Neg_RCLK_noedge_posedge,
                HoldLow         => tHold_REN1Neg_RCLK_noedge_posedge,
                CheckEnabled    => TRUE,
                RefTransition    => '/',
                HeaderMsg       => InstancePath & partID,
                TimingData      => TD_REN2Neg_RCLK,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_REN2Neg_RCLK);
              END IF;

              --9. REN1Neg/RSNeg setup time check (tRSS)
              IF REN1Neg'Event AND RSNeg'Event THEN
              VitalSetupHoldCheck (
                TestSignal      => REN1Neg,
                TestSignalName  => "REN1Neg",
                RefSignal       => RSNeg,
                RefSignalName   => "RSNeg",
                SetupLow        => tSetup_REN1Neg_RSNeg_noedge_posedge,
                CheckEnabled    => TRUE,
                RefTransition    => '/',
                HeaderMsg       => InstancePath & partID,
                TimingData      => TD_REN1Neg_RSNeg,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_REN1Neg_RSNeg);
              END IF;

              --10. REN2Neg/RSNeg setup time check (tRSS)
              IF REN2Neg'Event AND RSNeg'Event THEN
              VitalSetupHoldCheck (
                TestSignal      => REN2Neg,
                TestSignalName  => "REN2Neg",
                RefSignal       => RSNeg,
                RefSignalName   => "RSNeg",
                SetupLow        => tSetup_REN1Neg_RSNeg_noedge_posedge,
                CheckEnabled    => TRUE,
                RefTransition    => '/',
                HeaderMsg       => InstancePath & partID,
                TimingData      => TD_REN2Neg_RSNeg,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_REN2Neg_RSNeg);
              END IF;

              --11. WEN1Neg/RSNeg setup time check (tRSS)
              IF WEN1Neg'Event AND RSNeg'Event THEN
              VitalSetupHoldCheck (
                TestSignal      => WEN1Neg,
                TestSignalName  => "WEN1Neg",
                RefSignal       => RSNeg,
                RefSignalName   => "RSNeg",
                SetupLow        => tSetup_REN1Neg_RSNeg_noedge_posedge,
                CheckEnabled    => TRUE,
                RefTransition    => '/',
                HeaderMsg       => InstancePath & partID,
                TimingData      => TD_WEN1Neg_RSNeg,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_WEN1Neg_RSNeg);
              END IF;

              --12. WEN2LDNeg/RSNeg setup time check (tRSS)
              IF WEN2LDNeg'Event AND RSNeg'Event THEN
              VitalSetupHoldCheck (
                TestSignal      => WEN2LDNeg,
                TestSignalName  => "WEN2LDNeg",
                RefSignal       => RSNeg,
                RefSignalName   => "RSNeg",
                SetupLow        => tSetup_REN1Neg_RSNeg_noedge_posedge,
                CheckEnabled    => TRUE,
                RefTransition    => '/',
                HeaderMsg       => InstancePath & partID,
                TimingData      => TD_WEN2LDNeg_RSNeg,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_WEN2LDNeg_RSNeg);
              END IF;

              Violation :=
                Pviol_WCLK            OR
                Pviol_RCLK            OR
                Pviol_RSNeg           OR
                Tviol_D0_WCLK         OR
                Tviol_WEN1Neg_WCLK    OR
                Tviol_WEN2LDNeg_WCLK  OR
                Tviol_REN1Neg_RCLK    OR
                Tviol_REN2Neg_RCLK    OR
                Tviol_WEN1Neg_RSNeg   OR
                Tviol_WEN2LDNeg_RSNeg OR
                Tviol_REN1Neg_RSNeg   OR
                Tviol_REN2Neg_RSNeg   OR
                Rviol_REN1Neg_RSNeg   OR
                Rviol_REN2Neg_RSNeg   OR
                Rviol_WEN1Neg_RSNeg   OR
                Rviol_WEN2LDNeg_RSNeg;

              ASSERT   Violation = '0'
              REPORT   InstancePath & partID & " : signal values may be" &
                       " incorrect due timing violation(s)"
              SEVERITY Warning;

            END IF;

          END PROCESS TimingChecks;

          ---------------------------------------------------------------
          -- Functionality section
          ---------------------------------------------------------------

        MainReadWrite: PROCESS( RSNeg, WCLK, RCLK, WEN1Neg, WEN2LDNeg,
                          REN1Neg, REN2Neg, D, OENeg )
                VARIABLE FIFOMemory : FIFOArray := (FIFOArray'range =>
                                                FIFOWord'(OTHERS => 'X'));
              BEGIN
                IF RSNeg'Event AND RSNeg = '0' THEN
                  FFNeg_zd  <= '1';
                  PAFNeg_zd <= '1';
                  EFNeg_zd  <= '0';
                  PAENeg_zd <= '0';
                  Pointer <= 0;

                  IF OENeg = '0' THEN
                    Q_zd <= (OTHERS => '0');
                  ELSIF OENeg = '1' THEN
                    Q_zd <= (OTHERS => 'Z');
                  END IF;

                  Start <= '1';

                ELSIF Start = '1' THEN
                  IF WCLK'Event AND WCLK = '1' THEN