idt72t54242.ftm

VHDL的ram和fifo model code 包含众多的厂家

  (CELL (CELLTYPE "VITALbuf")
    (INSTANCE %LABEL%/FIFO3/SKEW3) (DELAY (ABSOLUTE (DEVICE(5:5:5))))
</TIMING></FMFTIME>
<FMFTIME>
IDT72T54242L6-7BB<SOURCE>Integrated Device Technology DSC-6158/2, March 2005</SOURCE>
<COMMENT>The Values listed are for VCC=2.35V to 2.65V, CL=10pF, Ta=0 to 70C Commercial,
-40 to +85 Industrial
For each parameter only minimum or maximum values were provided by the vendor, other values are derived</COMMENT>
<TIMING>
)
  (CELL
  (CELLTYPE "idt72t54242_onefifo")
  (INSTANCE %LABEL%/FIFO0)
  (DELAY (ABSOLUTE
  (IOPATH RCLK Q0 (0.6:2.2:3.8) (0.6:2.2:3.8) (1.3:2.6:3.8) (1.3:2.6:3.8) (1.3:2.6:3.8) (1.3:2.6:3.8))
    (IOPATH OENeg Q0 (0.8:2.3:3.8) (0.8:2.3:3.8) (0.8:2.3:3.8) (0.8:2.3:3.8) (0.8:2.3:3.8) (0.8:2.3:3.8))
    (IOPATH PDNeg Q0 (0) (0) (6.5:13.1:19.6) (4.5:9.1:13.7) (6.5:13.1:19.6) (4.5:9.1:13.7))
    (IOPATH MRSNeg EFNeg (5:10:15) (5:10:15))
    (IOPATH WCLK FFNeg (1.3:2.6:3.8) (1.3:2.6:3.8))
    (IOPATH RCLK EFNeg (1.2:2.5:3.8) (1.2:2.5:3.8))
    (COND sync (IOPATH WCLK PAFNeg (1.2:2.5:3.8) (1.2:2.5:3.8)))
    (COND sync (IOPATH RCLK PAENeg (1.2:2.5:3.8) (1.2:2.5:3.8)))
    (COND async (IOPATH WCLK PAFNeg (4:8:12) (4:8:12)))
    (COND async (IOPATH RCLK PAENeg (4:8:12) (4:8:12)))
    (IOPATH RCLK ERCLK (1.4:2.8:4.3) (1.4:2.8:4.3))
    (IOPATH RCLK ERENNeg (1.2:2.5:3.8) (1.2:2.5:3.8))
  ))
  (TIMINGCHECK
    (SETUP D0 WCLK (2:2:2))
    (SETUP RENNeg RCLK (2:2:2))
    (SETUP SI SCLK (15:15:15))
    (SETUP SWENNeg SCLK (5:5:5))
    (SETUP RENNeg MRSNeg (15:15:15))
    (HOLD D0 WCLK (0.5:0.5:0.5))
    (HOLD RENNeg RCLK (0.5:0.5:0.5))
    (HOLD SI SCLK (5:5:5))
    (HOLD SWENNeg SCLK (5:5:5))
    (HOLD RENNeg PDNeg (1000:1000:1000))
    (RECOVERY RENNeg MRSNeg (10:10:10))
    (WIDTH (negedge MRSNeg) (200:200:200))
    (WIDTH (COND SDR (negedge RCLK)) (2.8:2.8:2.8))
    (WIDTH (COND SDR (posedge RCLK)) (2.8:2.8:2.8))
    (WIDTH (COND DDR (negedge RCLK)) (6:6:6))
    (WIDTH (COND DDR (posedge RCLK)) (6:6:6))
    (WIDTH (negedge SCLK) (45:45:45))
    (WIDTH (posedge SCLK) (45:45:45))
    (WIDTH (negedge PDNeg) (19.6:19.6:19.6))
    (PERIOD (COND SDR (posedge RCLK)) (6.7:6.7:6.7))
    (PERIOD (COND DDR (posedge RCLK)) (13:13:13))
    (PERIOD (posedge SCLK) (100:100:100))
  ))
  (CELL (CELLTYPE "VITALbuf")
    (INSTANCE %LABEL%/FIFO0/SKEW1) (DELAY (ABSOLUTE (DEVICE(5:5:5)))))
  (CELL (CELLTYPE "VITALbuf")
    (INSTANCE %LABEL%/FIFO0/SKEW2) (DELAY (ABSOLUTE (DEVICE(6:6:6)))))
  (CELL (CELLTYPE "VITALbuf")
    (INSTANCE %LABEL%/FIFO0/SKEW3) (DELAY (ABSOLUTE (DEVICE(6:6:6)))))
    
    (CELL
  (CELLTYPE "idt72t54242_onefifo")
  (INSTANCE %LABEL%/FIFO1)
  (DELAY (ABSOLUTE
  (IOPATH RCLK Q0 (0.6:2.2:3.8) (0.6:2.2:3.8) (1.3:2.6:3.8) (1.3:2.6:3.8) (1.3:2.6:3.8) (1.3:2.6:3.8))
    (IOPATH OENeg Q0 (0.8:2.3:3.8) (0.8:2.3:3.8) (0.8:2.3:3.8) (0.8:2.3:3.8) (0.8:2.3:3.8) (0.8:2.3:3.8))
    (IOPATH PDNeg Q0 (0) (0) (6.5:13.1:19.6) (4.5:9.1:13.7) (6.5:13.1:19.6) (4.5:9.1:13.7))
    (IOPATH MRSNeg EFNeg (5:10:15) (5:10:15))
    (IOPATH WCLK FFNeg (1.3:2.6:3.8) (1.3:2.6:3.8))
    (IOPATH RCLK EFNeg (1.2:2.5:3.8) (1.2:2.5:3.8))
    (COND sync (IOPATH WCLK PAFNeg (1.2:2.5:3.8) (1.2:2.5:3.8)))
    (COND sync (IOPATH RCLK PAENeg (1.2:2.5:3.8) (1.2:2.5:3.8)))
    (COND async (IOPATH WCLK PAFNeg (4:8:12) (4:8:12)))
    (COND async (IOPATH RCLK PAENeg (4:8:12) (4:8:12)))
    (IOPATH RCLK ERCLK (1.4:2.8:4.3) (1.4:2.8:4.3))
    (IOPATH RCLK ERENNeg (1.2:2.5:3.8) (1.2:2.5:3.8))
  ))
  (TIMINGCHECK
    (SETUP D0 WCLK (2:2:2))
    (SETUP RENNeg RCLK (2:2:2))
    (SETUP SI SCLK (15:15:15))
    (SETUP SWENNeg SCLK (5:5:5))
    (SETUP RENNeg MRSNeg (15:15:15))
    (HOLD D0 WCLK (0.5:0.5:0.5))
    (HOLD RENNeg RCLK (0.5:0.5:0.5))
    (HOLD SI SCLK (5:5:5))
    (HOLD SWENNeg SCLK (5:5:5))
    (HOLD RENNeg PDNeg (1000:1000:1000))
    (RECOVERY RENNeg MRSNeg (10:10:10))
    (WIDTH (negedge MRSNeg) (200:200:200))
    (WIDTH (COND SDR (negedge RCLK)) (2.8:2.8:2.8))
    (WIDTH (COND SDR (posedge RCLK)) (2.8:2.8:2.8))
    (WIDTH (COND DDR (negedge RCLK)) (6:6:6))
    (WIDTH (COND DDR (posedge RCLK)) (6:6:6))
    (WIDTH (negedge SCLK) (45:45:45))
    (WIDTH (posedge SCLK) (45:45:45))
    (WIDTH (negedge PDNeg) (19.6:19.6:19.6))
    (PERIOD (COND SDR (posedge RCLK)) (6.7:6.7:6.7))
    (PERIOD (COND DDR (posedge RCLK)) (13:13:13))
    (PERIOD (posedge SCLK) (100:100:100))
  ))
  (CELL (CELLTYPE "VITALbuf")
    (INSTANCE %LABEL%/FIFO1/SKEW1) (DELAY (ABSOLUTE (DEVICE(5:5:5)))))
  (CELL (CELLTYPE "VITALbuf")
    (INSTANCE %LABEL%/FIFO1/SKEW2) (DELAY (ABSOLUTE (DEVICE(6:6:6)))))
  (CELL (CELLTYPE "VITALbuf")
    (INSTANCE %LABEL%/FIFO1/SKEW3) (DELAY (ABSOLUTE (DEVICE(6:6:6)))))
    
    (CELL
  (CELLTYPE "idt72t54242_onefifo")
  (INSTANCE %LABEL%/FIFO2)
  (DELAY (ABSOLUTE
  (IOPATH RCLK Q0 (0.6:2.2:3.8) (0.6:2.2:3.8) (1.3:2.6:3.8) (1.3:2.6:3.8) (1.3:2.6:3.8) (1.3:2.6:3.8))
    (IOPATH OENeg Q0 (0.8:2.3:3.8) (0.8:2.3:3.8) (0.8:2.3:3.8) (0.8:2.3:3.8) (0.8:2.3:3.8) (0.8:2.3:3.8))
    (IOPATH PDNeg Q0 (0) (0) (6.5:13.1:19.6) (4.5:9.1:13.7) (6.5:13.1:19.6) (4.5:9.1:13.7))
    (IOPATH MRSNeg EFNeg (5:10:15) (5:10:15))
    (IOPATH WCLK FFNeg (1.3:2.6:3.8) (1.3:2.6:3.8))
    (IOPATH RCLK EFNeg (1.2:2.5:3.8) (1.2:2.5:3.8))
    (COND sync (IOPATH WCLK PAFNeg (1.2:2.5:3.8) (1.2:2.5:3.8)))
    (COND sync (IOPATH RCLK PAENeg (1.2:2.5:3.8) (1.2:2.5:3.8)))
    (COND async (IOPATH WCLK PAFNeg (4:8:12) (4:8:12)))
    (COND async (IOPATH RCLK PAENeg (4:8:12) (4:8:12)))
    (IOPATH RCLK ERCLK (1.4:2.8:4.3) (1.4:2.8:4.3))
    (IOPATH RCLK ERENNeg (1.2:2.5:3.8) (1.2:2.5:3.8))
  ))
  (TIMINGCHECK
    (SETUP D0 WCLK (2:2:2))
    (SETUP RENNeg RCLK (2:2:2))
    (SETUP SI SCLK (15:15:15))
    (SETUP SWENNeg SCLK (5:5:5))
    (SETUP RENNeg MRSNeg (15:15:15))
    (HOLD D0 WCLK (0.5:0.5:0.5))
    (HOLD RENNeg RCLK (0.5:0.5:0.5))
    (HOLD SI SCLK (5:5:5))
    (HOLD SWENNeg SCLK (5:5:5))
    (HOLD RENNeg PDNeg (1000:1000:1000))
    (RECOVERY RENNeg MRSNeg (10:10:10))
    (WIDTH (negedge MRSNeg) (200:200:200))
    (WIDTH (COND SDR (negedge RCLK)) (2.8:2.8:2.8))
    (WIDTH (COND SDR (posedge RCLK)) (2.8:2.8:2.8))
    (WIDTH (COND DDR (negedge RCLK)) (6:6:6))
    (WIDTH (COND DDR (posedge RCLK)) (6:6:6))
    (WIDTH (negedge SCLK) (45:45:45))
    (WIDTH (posedge SCLK) (45:45:45))
    (WIDTH (negedge PDNeg) (19.6:19.6:19.6))
    (PERIOD (COND SDR (posedge RCLK)) (6.7:6.7:6.7))
    (PERIOD (COND DDR (posedge RCLK)) (13:13:13))
    (PERIOD (posedge SCLK) (100:100:100))
  ))
  (CELL (CELLTYPE "VITALbuf")
    (INSTANCE %LABEL%/FIFO2/SKEW1) (DELAY (ABSOLUTE (DEVICE(5:5:5)))))
  (CELL (CELLTYPE "VITALbuf")
    (INSTANCE %LABEL%/FIFO2/SKEW2) (DELAY (ABSOLUTE (DEVICE(6:6:6)))))
  (CELL (CELLTYPE "VITALbuf")
    (INSTANCE %LABEL%/FIFO2/SKEW3) (DELAY (ABSOLUTE (DEVICE(6:6:6)))))
    
    (CELL
  (CELLTYPE "idt72t54242_onefifo")
  (INSTANCE %LABEL%/FIFO3)
  (DELAY (ABSOLUTE
  (IOPATH RCLK Q0 (0.6:2.2:3.8) (0.6:2.2:3.8) (1.3:2.6:3.8) (1.3:2.6:3.8) (1.3:2.6:3.8) (1.3:2.6:3.8))
    (IOPATH OENeg Q0 (0.8:2.3:3.8) (0.8:2.3:3.8) (0.8:2.3:3.8) (0.8:2.3:3.8) (0.8:2.3:3.8) (0.8:2.3:3.8))
    (IOPATH PDNeg Q0 (0) (0) (6.5:13.1:19.6) (4.5:9.1:13.7) (6.5:13.1:19.6) (4.5:9.1:13.7))
    (IOPATH MRSNeg EFNeg (5:10:15) (5:10:15))
    (IOPATH WCLK FFNeg (1.3:2.6:3.8) (1.3:2.6:3.8))
    (IOPATH RCLK EFNeg (1.2:2.5:3.8) (1.2:2.5:3.8))
    (COND sync (IOPATH WCLK PAFNeg (1.2:2.5:3.8) (1.2:2.5:3.8)))
    (COND sync (IOPATH RCLK PAENeg (1.2:2.5:3.8) (1.2:2.5:3.8)))
    (COND async (IOPATH WCLK PAFNeg (4:8:12) (4:8:12)))
    (COND async (IOPATH RCLK PAENeg (4:8:12) (4:8:12)))
    (IOPATH RCLK ERCLK (1.4:2.8:4.3) (1.4:2.8:4.3))
    (IOPATH RCLK ERENNeg (1.2:2.5:3.8) (1.2:2.5:3.8))
  ))
  (TIMINGCHECK
    (SETUP D0 WCLK (2:2:2))
    (SETUP RENNeg RCLK (2:2:2))
    (SETUP SI SCLK (15:15:15))
    (SETUP SWENNeg SCLK (5:5:5))
    (SETUP RENNeg MRSNeg (15:15:15))
    (HOLD D0 WCLK (0.5:0.5:0.5))
    (HOLD RENNeg RCLK (0.5:0.5:0.5))
    (HOLD SI SCLK (5:5:5))
    (HOLD SWENNeg SCLK (5:5:5))
    (HOLD RENNeg PDNeg (1000:1000:1000))
    (RECOVERY RENNeg MRSNeg (10:10:10))
    (WIDTH (negedge MRSNeg) (200:200:200))
    (WIDTH (COND SDR (negedge RCLK)) (2.8:2.8:2.8))
    (WIDTH (COND SDR (posedge RCLK)) (2.8:2.8:2.8))
    (WIDTH (COND DDR (negedge RCLK)) (6:6:6))
    (WIDTH (COND DDR (posedge RCLK)) (6:6:6))
    (WIDTH (negedge SCLK) (45:45:45))
    (WIDTH (posedge SCLK) (45:45:45))
    (WIDTH (negedge PDNeg) (19.6:19.6:19.6))
    (PERIOD (COND SDR (posedge RCLK)) (6.7:6.7:6.7))
    (PERIOD (COND DDR (posedge RCLK)) (13:13:13))
    (PERIOD (posedge SCLK) (100:100:100))
  ))
  (CELL (CELLTYPE "VITALbuf")
    (INSTANCE %LABEL%/FIFO3/SKEW1) (DELAY (ABSOLUTE (DEVICE(5:5:5)))))
  (CELL (CELLTYPE "VITALbuf")
    (INSTANCE %LABEL%/FIFO3/SKEW2) (DELAY (ABSOLUTE (DEVICE(6:6:6)))))
  (CELL (CELLTYPE "VITALbuf")
    (INSTANCE %LABEL%/FIFO3/SKEW3) (DELAY (ABSOLUTE (DEVICE(6:6:6))))
  </TIMING></FMFTIME>
</BODY></FTML>