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📄 idt72t54242.ftm

📁 VHDL的ram和fifo model code 包含众多的厂家
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<!DOCTYPE FTML SYSTEM "ftml.dtd"><FTML><HEAD><TITLE>FMF Timing for idt72T54242 Parts</TITLE><BODY><REVISION.HISTORY>version: |  author:     | mod date: | changes made:  V1.0     S.Gmitrovic    05 Oct 14   Initial release</REVISION.HISTORY><TIMESCALE>1ns</TIMESCALE><MODEL>idt72t54242<FMFTIME>IDT72T54242L5BB<SOURCE>Integrated Device Technology DSC-6158/2, March 2005</SOURCE><COMMENT>The Values listed are for VCC=2.35V to 2.65V, CL=10pF, Ta=0 to 70C Commercial,-40 to +85 IndustrialFor each parameter only minimum or maximum values were provided by the vendor, other values are derived</COMMENT><TIMING>  )  (CELL  (CELLTYPE "idt72t54242_onefifo")  (INSTANCE %LABEL%/FIFO0)  (DELAY (ABSOLUTE    (IOPATH RCLK Q0 (0.6:2.1:3.6) (0.6:2.1:3.6) (1.2:2.4:3.6) (1.2:2.4:3.6) (1.2:2.4:3.6) (1.2:2.4:3.6))    (IOPATH OENeg Q0 (1.2:2.4:3.6) (1.2:2.4:3.6) (1.2:2.4:3.6) (1.2:2.4:3.6) (1.2:2.4:3.6) (1.2:2.4:3.6))    (IOPATH PDNeg Q0 (0) (0) (6.5:13:19.4) (4.5:9:13.5) (6.5:13:19.4) (4.5:9:13.5))    (IOPATH MRSNeg EFNeg (3:4:12) (3:4:12))    (IOPATH WCLK FFNeg (1.2:2.4:3.6) (1.2:2.4:3.6))    (IOPATH RCLK EFNeg (1.2:2.4:3.6) (1.2:2.4:3.6))    (COND sync (IOPATH WCLK PAFNeg (1.2:2.4:3.6) (1.2:2.4:3.6)))    (COND sync (IOPATH RCLK PAENeg (1.2:2.4:3.6) (1.2:2.4:3.6)))    (COND async (IOPATH WCLK PAFNeg (4:7:10) (4:7:10)))    (COND async (IOPATH RCLK PAENeg (4:7:10) (4:7:10)))    (IOPATH RCLK ERCLK (1.3:2.6:4.0) (1.3:2.6:4.0))    (IOPATH RCLK ERENNeg (1.2:2.4:3.6) (1.2:2.4:3.6))  ))  (TIMINGCHECK    (SETUP D0 WCLK (1.5:1.5:1.5))    (SETUP RENNeg RCLK (1.5:1.5:1.5))    (SETUP SI SCLK (15:15:15))    (SETUP SWENNeg SCLK (5:5:5))    (SETUP RENNeg MRSNeg (15:15:15))    (HOLD D0 WCLK (0.5:0.5:0.5))    (HOLD RENNeg RCLK (0.5:0.5:0.5))    (HOLD SI SCLK (5:5:5))    (HOLD SWENNeg SCLK (5:5:5))    (HOLD RENNeg PDNeg (1000:1000:1000))    (RECOVERY RENNeg MRSNeg (10:10:10))    (WIDTH (negedge MRSNeg) (200:200:200))    (WIDTH (COND SDR (negedge RCLK)) (2.3:2.3:2.3))    (WIDTH (COND SDR (posedge RCLK)) (2.3:2.3:2.3))    (WIDTH (COND DDR (negedge RCLK)) (4.5:4.5:4.5))    (WIDTH (COND DDR (posedge RCLK)) (4.5:4.5:4.5))    (WIDTH (negedge SCLK) (45:45:45))    (WIDTH (posedge SCLK) (45:45:45))    (WIDTH (negedge PDNeg) (19.4:19.4:19.4))    (PERIOD (COND SDR (posedge RCLK)) (5:5:5))    (PERIOD (COND DDR (posedge RCLK)) (10:10:10))    (PERIOD (posedge SCLK) (100:100:100))  ))  (CELL (CELLTYPE "VITALbuf")    (INSTANCE %LABEL%/FIFO0/SKEW1) (DELAY (ABSOLUTE (DEVICE(4:4:4)))))  (CELL (CELLTYPE "VITALbuf")    (INSTANCE %LABEL%/FIFO0/SKEW2) (DELAY (ABSOLUTE (DEVICE(4:4:4)))))  (CELL (CELLTYPE "VITALbuf")    (INSTANCE %LABEL%/FIFO0/SKEW3) (DELAY (ABSOLUTE (DEVICE(5:5:5)))))      (CELL  (CELLTYPE "idt72t54242_onefifo")  (INSTANCE %LABEL%/FIFO1)  (DELAY (ABSOLUTE    (IOPATH RCLK Q0 (0.6:2.1:3.6) (0.6:2.1:3.6) (1.2:2.4:3.6) (1.2:2.4:3.6) (1.2:2.4:3.6) (1.2:2.4:3.6))    (IOPATH OENeg Q0 (1.2:2.4:3.6) (1.2:2.4:3.6) (1.2:2.4:3.6) (1.2:2.4:3.6) (1.2:2.4:3.6) (1.2:2.4:3.6))    (IOPATH PDNeg Q0 (0) (0) (6.5:13:19.4) (4.5:9:13.5) (6.5:13:19.4) (4.5:9:13.5))    (IOPATH MRSNeg EFNeg (3:4:12) (3:4:12))    (IOPATH WCLK FFNeg (1.2:2.4:3.6) (1.2:2.4:3.6))    (IOPATH RCLK EFNeg (1.2:2.4:3.6) (1.2:2.4:3.6))    (COND sync (IOPATH WCLK PAFNeg (1.2:2.4:3.6) (1.2:2.4:3.6)))    (COND sync (IOPATH RCLK PAENeg (1.2:2.4:3.6) (1.2:2.4:3.6)))    (COND async (IOPATH WCLK PAFNeg (4:7:10) (4:7:10)))    (COND async (IOPATH RCLK PAENeg (4:7:10) (4:7:10)))    (IOPATH RCLK ERCLK (1.3:2.6:4.0) (1.3:2.6:4.0))    (IOPATH RCLK ERENNeg (1.2:2.4:3.6) (1.2:2.4:3.6))  ))  (TIMINGCHECK    (SETUP D0 WCLK (1.5:1.5:1.5))    (SETUP RENNeg RCLK (1.5:1.5:1.5))    (SETUP SI SCLK (15:15:15))    (SETUP SWENNeg SCLK (5:5:5))    (SETUP RENNeg MRSNeg (15:15:15))    (HOLD D0 WCLK (0.5:0.5:0.5))    (HOLD RENNeg RCLK (0.5:0.5:0.5))    (HOLD SI SCLK (5:5:5))    (HOLD SWENNeg SCLK (5:5:5))    (HOLD RENNeg PDNeg (1000:1000:1000))    (RECOVERY RENNeg MRSNeg (10:10:10))    (WIDTH (negedge MRSNeg) (200:200:200))    (WIDTH (COND SDR (negedge RCLK)) (2.3:2.3:2.3))    (WIDTH (COND SDR (posedge RCLK)) (2.3:2.3:2.3))    (WIDTH (COND DDR (negedge RCLK)) (4.5:4.5:4.5))    (WIDTH (COND DDR (posedge RCLK)) (4.5:4.5:4.5))    (WIDTH (negedge SCLK) (45:45:45))    (WIDTH (posedge SCLK) (45:45:45))    (WIDTH (negedge PDNeg) (19.4:19.4:19.4))    (PERIOD (COND SDR (posedge RCLK)) (5:5:5))    (PERIOD (COND DDR (posedge RCLK)) (10:10:10))    (PERIOD (posedge SCLK) (100:100:100))  ))  (CELL (CELLTYPE "VITALbuf")    (INSTANCE %LABEL%/FIFO1/SKEW1) (DELAY (ABSOLUTE (DEVICE(4:4:4)))))  (CELL (CELLTYPE "VITALbuf")    (INSTANCE %LABEL%/FIFO1/SKEW2) (DELAY (ABSOLUTE (DEVICE(4:4:4)))))  (CELL (CELLTYPE "VITALbuf")    (INSTANCE %LABEL%/FIFO1/SKEW3) (DELAY (ABSOLUTE (DEVICE(5:5:5)))))    (CELL  (CELLTYPE "idt72t54242_onefifo")  (INSTANCE %LABEL%/FIFO2)  (DELAY (ABSOLUTE    (IOPATH RCLK Q0 (0.6:2.1:3.6) (0.6:2.1:3.6) (1.2:2.4:3.6) (1.2:2.4:3.6) (1.2:2.4:3.6) (1.2:2.4:3.6))    (IOPATH OENeg Q0 (1.2:2.4:3.6) (1.2:2.4:3.6) (1.2:2.4:3.6) (1.2:2.4:3.6) (1.2:2.4:3.6) (1.2:2.4:3.6))    (IOPATH PDNeg Q0 (0) (0) (6.5:13:19.4) (4.5:9:13.5) (6.5:13:19.4) (4.5:9:13.5))    (IOPATH MRSNeg EFNeg (3:4:12) (3:4:12))    (IOPATH WCLK FFNeg (1.2:2.4:3.6) (1.2:2.4:3.6))    (IOPATH RCLK EFNeg (1.2:2.4:3.6) (1.2:2.4:3.6))    (COND sync (IOPATH WCLK PAFNeg (1.2:2.4:3.6) (1.2:2.4:3.6)))    (COND sync (IOPATH RCLK PAENeg (1.2:2.4:3.6) (1.2:2.4:3.6)))    (COND async (IOPATH WCLK PAFNeg (4:7:10) (4:7:10)))    (COND async (IOPATH RCLK PAENeg (4:7:10) (4:7:10)))    (IOPATH RCLK ERCLK (1.3:2.6:4.0) (1.3:2.6:4.0))    (IOPATH RCLK ERENNeg (1.2:2.4:3.6) (1.2:2.4:3.6))  ))  (TIMINGCHECK    (SETUP D0 WCLK (1.5:1.5:1.5))    (SETUP RENNeg RCLK (1.5:1.5:1.5))    (SETUP SI SCLK (15:15:15))    (SETUP SWENNeg SCLK (5:5:5))    (SETUP RENNeg MRSNeg (15:15:15))    (HOLD D0 WCLK (0.5:0.5:0.5))    (HOLD RENNeg RCLK (0.5:0.5:0.5))    (HOLD SI SCLK (5:5:5))    (HOLD SWENNeg SCLK (5:5:5))    (HOLD RENNeg PDNeg (1000:1000:1000))    (RECOVERY RENNeg MRSNeg (10:10:10))    (WIDTH (negedge MRSNeg) (200:200:200))    (WIDTH (COND SDR (negedge RCLK)) (2.3:2.3:2.3))    (WIDTH (COND SDR (posedge RCLK)) (2.3:2.3:2.3))    (WIDTH (COND DDR (negedge RCLK)) (4.5:4.5:4.5))    (WIDTH (COND DDR (posedge RCLK)) (4.5:4.5:4.5))    (WIDTH (negedge SCLK) (45:45:45))    (WIDTH (posedge SCLK) (45:45:45))    (WIDTH (negedge PDNeg) (19.4:19.4:19.4))    (PERIOD (COND SDR (posedge RCLK)) (5:5:5))    (PERIOD (COND DDR (posedge RCLK)) (10:10:10))    (PERIOD (posedge SCLK) (100:100:100))  ))  (CELL (CELLTYPE "VITALbuf")    (INSTANCE %LABEL%/FIFO2/SKEW1) (DELAY (ABSOLUTE (DEVICE(4:4:4)))))  (CELL (CELLTYPE "VITALbuf")    (INSTANCE %LABEL%/FIFO2/SKEW2) (DELAY (ABSOLUTE (DEVICE(4:4:4)))))  (CELL (CELLTYPE "VITALbuf")    (INSTANCE %LABEL%/FIFO2/SKEW3) (DELAY (ABSOLUTE (DEVICE(5:5:5)))))        (CELL  (CELLTYPE "idt72t54242_onefifo")  (INSTANCE %LABEL%/FIFO3)  (DELAY (ABSOLUTE    (IOPATH RCLK Q0 (0.6:2.1:3.6) (0.6:2.1:3.6) (1.2:2.4:3.6) (1.2:2.4:3.6) (1.2:2.4:3.6) (1.2:2.4:3.6))    (IOPATH OENeg Q0 (1.2:2.4:3.6) (1.2:2.4:3.6) (1.2:2.4:3.6) (1.2:2.4:3.6) (1.2:2.4:3.6) (1.2:2.4:3.6))    (IOPATH PDNeg Q0 (0) (0) (6.5:13:19.4) (4.5:9:13.5) (6.5:13:19.4) (4.5:9:13.5))    (IOPATH MRSNeg EFNeg (3:4:12) (3:4:12))    (IOPATH WCLK FFNeg (1.2:2.4:3.6) (1.2:2.4:3.6))    (IOPATH RCLK EFNeg (1.2:2.4:3.6) (1.2:2.4:3.6))    (COND sync (IOPATH WCLK PAFNeg (1.2:2.4:3.6) (1.2:2.4:3.6)))    (COND sync (IOPATH RCLK PAENeg (1.2:2.4:3.6) (1.2:2.4:3.6)))    (COND async (IOPATH WCLK PAFNeg (4:7:10) (4:7:10)))    (COND async (IOPATH RCLK PAENeg (4:7:10) (4:7:10)))    (IOPATH RCLK ERCLK (1.3:2.6:4.0) (1.3:2.6:4.0))    (IOPATH RCLK ERENNeg (1.2:2.4:3.6) (1.2:2.4:3.6))  ))  (TIMINGCHECK    (SETUP D0 WCLK (1.5:1.5:1.5))    (SETUP RENNeg RCLK (1.5:1.5:1.5))    (SETUP SI SCLK (15:15:15))    (SETUP SWENNeg SCLK (5:5:5))    (SETUP RENNeg MRSNeg (15:15:15))    (HOLD D0 WCLK (0.5:0.5:0.5))    (HOLD RENNeg RCLK (0.5:0.5:0.5))    (HOLD SI SCLK (5:5:5))    (HOLD SWENNeg SCLK (5:5:5))    (HOLD RENNeg PDNeg (1000:1000:1000))    (RECOVERY RENNeg MRSNeg (10:10:10))    (WIDTH (negedge MRSNeg) (200:200:200))    (WIDTH (COND SDR (negedge RCLK)) (2.3:2.3:2.3))    (WIDTH (COND SDR (posedge RCLK)) (2.3:2.3:2.3))    (WIDTH (COND DDR (negedge RCLK)) (4.5:4.5:4.5))    (WIDTH (COND DDR (posedge RCLK)) (4.5:4.5:4.5))    (WIDTH (negedge SCLK) (45:45:45))    (WIDTH (posedge SCLK) (45:45:45))    (WIDTH (negedge PDNeg) (19.4:19.4:19.4))    (PERIOD (COND SDR (posedge RCLK)) (5:5:5))    (PERIOD (COND DDR (posedge RCLK)) (10:10:10))    (PERIOD (posedge SCLK) (100:100:100))  ))  (CELL (CELLTYPE "VITALbuf")    (INSTANCE %LABEL%/FIFO3/SKEW1) (DELAY (ABSOLUTE (DEVICE(4:4:4)))))  (CELL (CELLTYPE "VITALbuf")    (INSTANCE %LABEL%/FIFO3/SKEW2) (DELAY (ABSOLUTE (DEVICE(4:4:4)))))

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