idt72v815.ftm
来自「VHDL的ram和fifo model code 包含众多的厂家」· FTM 代码 · 共 120 行
FTM
120 行
<!DOCTYPE FTML SYSTEM "ftml.dtd"><FTML><HEAD><TITLE>FMF Timing for IDT72V815 Parts</TITLE><REVISION.HISTORY>version: | author: | mod date: | changes made: V1.0 R. Munden 99 JUN 22 Initial release</REVISION.HISTORY></HEAD><BODY><TIMESCALE>1ns</TIMESCALE><MODEL>IDT72V815<FMFTIME>IDT72V815L10PF<SOURCE>IDT data sheet August 1998</SOURCE><COMMENT>The Values listed are for VCC=3.0V to 3.6V, CL=30pF, Ta=0 to 70 Celsius</COMMENT><COMMENT>Typical values are derived</COMMENT><COMMENT>No value found for tLDH</COMMENT><TIMING> (DELAY (ABSOLUTE (IOPATH RCLK Q0 (2:5:6.5) (2:5:6.5) (2:5:6.5) (2:5:6.5) (2:5:6.5) (2:5:6.5)) (IOPATH RSNeg Q0 (3:8:15) (3:8:15) (3:8:15) (3:8:15) (3:8:15) (3:8:15)) (IOPATH RSNeg EFORNeg (3:8:15) (3:8:15)) (IOPATH OENeg Q0 (1:5:6) (1:5:6) (1:5:6) (0:5:6) (1:5:6) (0:5:6)) (IOPATH WCLK FFIRNeg (2:5:6.5) (2:5:6.5)) (IOPATH RCLK EFORNeg (2:5:6.5) (2:5:6.5)) (IOPATH RCLK PAFNeg (3:9:17) (3:9:17)) (IOPATH WCLK PAFNeg (3:6:8) (3:6:8)) (IOPATH RCLK PAENeg (3:9:17) (3:9:17)) (IOPATH WCLK PAENeg (3:6:8) (3:6:8)) (IOPATH RCLK WXOHFNeg (3:9:17) (3:9:17)) (IOPATH RCLK RXONeg (2:5:6.5) (2:5:6.5)) )) (TIMINGCHECK (PERIOD (posedge RCLK) (10)) (WIDTH (posedge RCLK) (4.5)) (WIDTH (negedge RCLK) (4.5)) (WIDTH (negedge RSNeg) (10)) (WIDTH (negedge RXINeg) (3)) (SETUPHOLD D0 (posedge WCLK) (3) (0.5)) (SETUPHOLD RENNeg (posedge RCLK) (3) (0.5)) (SETUP LDNeg (posedge RSNeg) (8)) (SETUP RXINeg (posedge RCLK) (3)) )) (CELL (CELLTYPE "VITALbuf") (INSTANCE %LABEL%/SKEW1) (DELAY (ABSOLUTE ( DEVICE (5) ) ) ) ) (CELL (CELLTYPE "VITALbuf" ) (INSTANCE %LABEL%/SKEW2) (DELAY (ABSOLUTE ( DEVICE (14) ) ) )</TIMING></FMFTIME><FMFTIME>IDT72V815L15PF<SOURCE>IDT data sheet August 1998</SOURCE><COMMENT>The Values listed are for VCC=3.0V to 3.6V, CL=30pF, Ta=0 to 70 Celsius</COMMENT><COMMENT>Typical values are derived</COMMENT><COMMENT>No value found for tLDH</COMMENT><TIMING> (DELAY (ABSOLUTE (IOPATH RCLK Q0 (2:6:10)(2:6:10)(2:6:10)(2:6:10)(2:6:10)(2:6:10)) (IOPATH RSNeg Q0 (3:10:15) (3:10:15) (3:10:15) (3:10:15) (3:10:15) (3:10:15)) (IOPATH RSNeg EFORNeg (3:10:15) (3:10:15)) (IOPATH OENeg Q0 (3:6:8) (3:6:8) (3:6:8) (0:6:8) (3:6:8) (0:6:8)) (IOPATH WCLK FFIRNeg (2:6:10) (2:6:10)) (IOPATH RCLK EFORNeg (2:6:10) (2:6:10)) (IOPATH RCLK PAFNeg (4:12:20) (5:12:20)) (IOPATH WCLK PAFNeg (4:8:10) (4:8:10)) (IOPATH RCLK PAENeg (4:12:20) (4:12:20)) (IOPATH WCLK PAENeg (4:8:10) (4:8:10)) (IOPATH RCLK WXOHFNeg (4:12:20) (4:12:20)) (IOPATH RCLK RXONeg (2:6:10) (2:6:10)) )) (TIMINGCHECK (PERIOD (posedge RCLK) (15)) (WIDTH (posedge RCLK) (6)) (WIDTH (negedge RCLK) (6)) (WIDTH (negedge RSNeg) (15)) (WIDTH (negedge RXINeg) (6.5)) (SETUPHOLD D0 (posedge WCLK) (4) (1)) (SETUPHOLD RENNeg (posedge RCLK) (4) (1)) (SETUP LDNeg (posedge RSNeg) (10)) (SETUP RXINeg (posedge RCLK) (5)) )) (CELL (CELLTYPE "VITALbuf") (INSTANCE %LABEL%/SKEW1) (DELAY (ABSOLUTE ( DEVICE (6) ) ) ) ) (CELL (CELLTYPE "VITALbuf" ) (INSTANCE %LABEL%/SKEW2) (DELAY (ABSOLUTE ( DEVICE (18) ) ) )</TIMING></FMFTIME><FMFTIME>IDT72V815L20PF<SOURCE>IDT data sheet August 1998</SOURCE><COMMENT>The Values listed are for VCC=3.0V to 3.6V, CL=30pF, Ta=0 to 70 Celsius</COMMENT><COMMENT>Typical values are derived</COMMENT><COMMENT>No value found for tLDH</COMMENT><TIMING> (DELAY (ABSOLUTE (IOPATH RCLK Q0 (2:8:12) (2:8:12) (2:8:12) (2:8:12) (2:8:12) (2:8:12)) (IOPATH RSNeg Q0 (4:13:20) (4:13:20) (4:13:20) (4:13:20) (4:13:20) (4:13:20)) (IOPATH RSNeg EFORNeg (4:13:20) (4:13:20)) (IOPATH OENeg Q0 (3:7:10) (3:7:10) (3:7:10) (0:7:10) (3:7:10) (0:7:10)) (IOPATH WCLK FFIRNeg (3:8:12) (3:8:12)) (IOPATH RCLK EFORNeg (3:8:12) (3:8:12)) (IOPATH RCLK PAFNeg (5:15:22) (5:15:22)) (IOPATH WCLK PAFNeg (4:8:12) (4:8:12)) (IOPATH RCLK PAENeg (5:15:22) (5:15:22)) (IOPATH WCLK PAENeg (4:8:12) (4:8:12)) (IOPATH RCLK WXOHFNeg (5:15:22) (5:15:22)) (IOPATH RCLK RXONeg (4:8:12) (4:8:12)) )) (TIMINGCHECK (PERIOD (posedge RCLK) (20)) (WIDTH (posedge RCLK) (8)) (WIDTH (negedge RCLK) (8)) (WIDTH (negedge RSNeg) (20)) (WIDTH (negedge RXINeg) (8)) (SETUPHOLD D0 (posedge WCLK) (5) (1)) (SETUPHOLD RENNeg (posedge RCLK) (5) (1)) (SETUP LDNeg (posedge RSNeg) (12)) (SETUP RXINeg (posedge RCLK) (8)) )) (CELL (CELLTYPE "VITALbuf") (INSTANCE %LABEL%/SKEW1) (DELAY (ABSOLUTE ( DEVICE (8) ) ) ) ) (CELL (CELLTYPE "VITALbuf" ) (INSTANCE %LABEL%/SKEW2) (DELAY (ABSOLUTE ( DEVICE (20) ) ) )</TIMING></FMFTIME></BODY></FTML>⌨️ 快捷键说明
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