idt723626.vhd

VHDL的ram和fifo model code 包含众多的厂家

      VARIABLE Tviol_FS0SD_MRS1Neg : X01 := '0';
      VARIABLE TD_FS0SD_MRS1Neg    : VitalTimingDataType;

      VARIABLE Tviol_FS1SEN_MRS1Neg: X01 := '0';
      VARIABLE TD_FS1SEN_MRS1Neg   : VitalTimingDataType;

      VARIABLE Tviol_FS0SD_MRS2Neg : X01 := '0';
      VARIABLE TD_FS0SD_MRS2Neg    : VitalTimingDataType;

      VARIABLE Tviol_FS1SEN_MRS2Neg: X01 := '0';
      VARIABLE TD_FS1SEN_MRS2Neg   : VitalTimingDataType;

      VARIABLE Tviol_BEFWFT_MRS1Neg: X01 := '0';
      VARIABLE TD_BEFWFT_MRS1Neg   : VitalTimingDataType;

      VARIABLE Tviol_BEFWFT_MRS2Neg: X01 := '0';
      VARIABLE TD_BEFWFT_MRS2Neg   : VitalTimingDataType;

      VARIABLE Tviol_SPMNeg_MRS1Neg: X01 := '0';
      VARIABLE TD_SPMNeg_MRS1Neg   : VitalTimingDataType;

      VARIABLE Tviol_SPMNeg_MRS2Neg: X01 := '0';
      VARIABLE TD_SPMNeg_MRS2Neg   : VitalTimingDataType;

      VARIABLE Tviol_FS0SD_CLKA    : X01 := '0';
      VARIABLE TD_FS0SD_CLKA       : VitalTimingDataType;

      VARIABLE Tviol_FS1SEN_CLKA   : X01 := '0';
      VARIABLE TD_FS1SEN_CLKA      : VitalTimingDataType;

      VARIABLE Tviol_BEFWFT_CLKA   : X01 := '0';
      VARIABLE TD_BEFWFT_CLKA      : VitalTimingDataType;

    -- Violation variable (used to OR all individual violation variables)

      VARIABLE Violation           : X01 := '0';
    
BEGIN

--------------------------------------------------------------------------------
-- Timing Check Section                                                       --
--------------------------------------------------------------------------------
 IF  (TimingChecksOn)
 THEN

      -- CLKA period and pulse width check(high & low)

      VitalPeriodPulseCheck (
          TestSignal      => CLKA,
          TestSignalName  => "CLKA",
          Period	  => tCLK,
          PulseWidthHigh  => tCLKH,
          PulseWidthLow   => tCLKL,
          CheckEnabled    => TRUE,
          HeaderMsg       => InstancePath & partID,
          PeriodData      => PD_CLKA,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Pviol_CLKA);

      -- CLKB period and pulse width check(high & low)

      VitalPeriodPulseCheck (
          TestSignal      => CLKB,
          TestSignalName  => "CLKB",
          Period	  => tCLK,
          PulseWidthHigh  => tCLKH,
          PulseWidthLow   => tCLKL,
          CheckEnabled    => TRUE,
          HeaderMsg       => InstancePath & partID,
          PeriodData      => PD_CLKB,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Pviol_CLKB);

      -- CLKC period and pulse width check(high & low)

      VitalPeriodPulseCheck (
          TestSignal      => CLKC,
          TestSignalName  => "CLKC",
          Period	  => tCLK,
          PulseWidthHigh  => tCLKH,
          PulseWidthLow   => tCLKL,
          CheckEnabled    => TRUE,
          HeaderMsg       => InstancePath & partID,
          PeriodData      => PD_CLKC,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Pviol_CLKC);

      -- A/CLKA setup/hold time checks

      VitalSetupHoldCheck (
          TestSignal      => A_ipd,
          TestSignalName  => "A",
          RefSignal       => CLKA,
          RefSignalName   => "CLKA",
          SetupHigh       => tDS,
          SetupLow        => tDS,
          HoldHigh        => tDH,
          HoldLow         => tDH,
          CheckEnabled    => (CSANeg = '0') AND (WRA = '1') 
                              AND (ENA = '1'),
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_A0_CLKA,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Tviol_A0_CLKA);

   -- C/CLKC setup/hold time checks

      VitalSetupHoldCheck (
          TestSignal      => C,
          TestSignalName  => "C",
          RefSignal       => CLKC,
          RefSignalName   => "CLKC",
          SetupHigh       => tDS,
          SetupLow        => tDS,
          HoldHigh        => tDH,
          HoldLow         => tDH,
          CheckEnabled    => WENC = '1',
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_C0_CLKC,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => TViol_C0_CLKC);

      -- CSANeg/CLKA setup/hold time check

      VitalSetupHoldCheck (
          TestSignal      => CSANeg,
          TestSignalName  => "CSANeg",
          RefSignal       => CLKA,
          RefSignalName   => "CLKA",
          SetupLow        => tENS,
          SetupHigh       => tENS,
          HoldLow         => tENH,
          HoldHigh        => tENH,
          CheckEnabled    => True,
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_CSANeg_CLKA,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Tviol_CSANeg_CLKA);

      -- WRA/CLKA setup/hold time check

      VitalSetupHoldCheck (
          TestSignal      => WRA,
          TestSignalName  => "WRA",
          RefSignal       => CLKA,
          RefSignalName   => "CLKA",
          SetupHigh       => tENS,
          SetupLow        => tENS,
          HoldHigh        => tENH,
          HoldLow         => tENH,
          CheckEnabled    => True,
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_WRA_CLKA,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Tviol_WRA_CLKA);

      -- ENA/CLKA setup/hold time check

      VitalSetupHoldCheck (
          TestSignal      => ENA,
          TestSignalName  => "ENA",
          RefSignal       => CLKA,
          RefSignalName   => "CLKA",
          SetupHigh       => tENS,
          SetupLow        => tENS,
          HoldHigh        => tENH,
          HoldLow         => tENH,
          CheckEnabled    => True,
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_ENA_CLKA,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Tviol_ENA_CLKA);

      -- MBA/CLKA setup/hold time check

      VitalSetupHoldCheck (
          TestSignal      => MBA,
          TestSignalName  => "MBA",
          RefSignal       => CLKA,
          RefSignalName   => "CLKA",
          SetupHigh       => tENS,
          SetupLow        => tENS,
          HoldHigh        => tENH,
          HoldLow         => tENH,
          CheckEnabled    => True,
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_MBA_CLKA,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Tviol_MBA_CLKA);

      -- RENB/CLKB setup/hold time check

      VitalSetupHoldCheck (
          TestSignal      => RENB,
          TestSignalName  => "RENB",
          RefSignal       => CLKB,
          RefSignalName   => "CLKB",
          SetupHigh       => tENS,
          SetupLow        => tENS,
          HoldHigh        => tENH,
          HoldLow         => tENH,
          CheckEnabled    => True,
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_RENB_CLKB,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Tviol_RENB_CLKB);

      -- MBB/CLKB setup/hold time check

      VitalSetupHoldCheck (
          TestSignal      => MBB,
          TestSignalName  => "MBB",
          RefSignal       => CLKB,
          RefSignalName   => "CLKB",
          SetupHigh       => tENS,
          SetupLow        => tENS,
          HoldHigh        => tENH,
          HoldLow         => tENH,
          CheckEnabled    => True,
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_MBB_CLKB,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Tviol_MBB_CLKB);

      -- WENC/CLKC setup/hold time check

      VitalSetupHoldCheck (
          TestSignal      => WENC,
          TestSignalName  => "WENC",
          RefSignal       => CLKC,
          RefSignalName   => "CLKC",
          SetupHigh       => tENS,
          SetupLow        => tENS,
          HoldHigh        => tENH,
          HoldLow         => tENH,
          CheckEnabled    => True,
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_WENC_CLKC,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Tviol_WENC_CLKC);

      -- MBC/CLKC setup/hold time check

      VitalSetupHoldCheck (
          TestSignal      => MBC,
          TestSignalName  => "MBC",
          RefSignal       => CLKC,
          RefSignalName   => "CLKC",
          SetupHigh       => tENS,
          SetupLow        => tENS,
          HoldHigh        => tENH,
          HoldLow         => tENH,
          CheckEnabled    => True,
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_MBC_CLKC,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Tviol_MBC_CLKC);

      -- MRS1Neg/CLKA setup/hold time check

      VitalSetupHoldCheck (
          TestSignal      => MRS1Neg,
          TestSignalName  => "MRS1Neg",
          RefSignal       => CLKA,
          RefSignalName   => "CLKA",
          SetupHigh       => tRSTS,
          SetupLow        => tRSTS,
          HoldHigh        => tRSTH,
          HoldLow         => tRSTH,
          CheckEnabled    => True,
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_MRS1Neg_CLKA,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Tviol_MRS1Neg_CLKA);

      -- MRS1Neg/CLKB setup/hold time check

      VitalSetupHoldCheck (
          TestSignal      => MRS1Neg,
          TestSignalName  => "MRS1Neg",
          RefSignal       => CLKB,
          RefSignalName   => "CLKB",
          SetupHigh       => tRSTS,
          SetupLow        => tRSTS,
          HoldHigh        => tRSTH,
          HoldLow         => tRSTH,
          CheckEnabled    => True,
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_MRS1Neg_CLKB,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Tviol_MRS1Neg_CLKB);

      -- MRS2Neg/CLKA setup/hold time check

      VitalSetupHoldCheck (
          TestSignal      => MRS2Neg,
          TestSignalName  => "MRS2Neg",
          RefSignal       => CLKA,
          RefSignalName   => "CLKA",
          SetupHigh       => tRSTS,
          SetupLow        => tRSTS,
          HoldHigh        => tRSTH,
          HoldLow         => tRSTH,
          CheckEnabled    => True,
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_MRS2Neg_CLKA,
          XOn             => XOn,