idt723626.vhd

VHDL的ram和fifo model code 包含众多的厂家

    A(20)   	=> A20,
    A(21)   	=> A21,
    A(22)   	=> A22,
    A(23)   	=> A23,
    A(24)   	=> A24,
    A(25)   	=> A25,
    A(26)   	=> A26,
    A(27)   	=> A27,
    A(28)   	=> A28,
    A(29)   	=> A29,
    A(30)   	=> A30,
    A(31)   	=> A31,
    A(32)   	=> A32,
    A(33)   	=> A33,
    A(34)   	=> A34,
    A(35)    	=> A35,
    AEANeg  	=> AEANeg,
    AEBNeg   	=> AEBNeg,
    AFANeg   	=> AFANeg,
    AFCNeg   	=> AFCNeg,
    B(0)       	=> B0,
    B(1)       	=> B1,
    B(2)       	=> B2,
    B(3)       	=> B3,
    B(4)       	=> B4,
    B(5)       	=> B5,
    B(6)       	=> B6,
    B(7)       	=> B7,
    B(8)       	=> B8,
    B(9)       	=> B9,
    B(10)      	=> B10,
    B(11)      	=> B11,
    B(12)      	=> B12,
    B(13)      	=> B13,
    B(14)      	=> B14,
    B(15)      	=> B15,
    B(16)      	=> B16,
    B(17)      	=> B17,
    BEFWFT   	=> BEFWFT_ipd,
    C(0)   	=> C0_ipd, 
    C(1)   	=> C1_ipd,
    C(2)   	=> C2_ipd,
    C(3)   	=> C3_ipd,
    C(4)   	=> C4_ipd,
    C(5)   	=> C5_ipd,
    C(6)   	=> C6_ipd,
    C(7)   	=> C7_ipd,
    C(8)   	=> C8_ipd,
    C(9)   	=> C9_ipd,
    C(10)  	=> C10_ipd,
    C(11)  	=> C11_ipd,
    C(12)  	=> C12_ipd,
    C(13)  	=> C13_ipd,
    C(14)  	=> C14_ipd,
    C(15)  	=> C15_ipd,
    C(16)  	=> C16_ipd,
    C(17)  	=> C17_ipd,
    CLKA        => CLKA_ipd,
    CLKB        => CLKB_ipd,
    CLKC        => CLKC_ipd,
    CSANeg      => CSANeg_ipd,
    CSBNeg      => CSBNeg_ipd,
    EFAORA   	=> EFAORA,
    EFBORB   	=> EFBORB,
    ENA         => ENA_ipd,
    FFAIRA   	=> FFAIRA,
    FFCIRC   	=> FFCIRC,
    FS0SD       => FS0SD_ipd,
    FS1SEN      => FS1SEN_ipd,
    MBA         => MBA_ipd,
    MBB         => MBB_ipd,
    MBC         => MBC_ipd,
    MBF1Neg     => MBF1Neg,
    MBF2Neg     => MBF2Neg,
    MRS1Neg     => MRS1Neg_ipd,
    MRS2Neg     => MRS2Neg_ipd,
    PRS1Neg     => PRS1Neg_ipd,
    PRS2Neg     => PRS2Neg_ipd,
    RENB        => RENB_ipd,
    SIZEB       => SIZEB_ipd,
    SIZEC       => SIZEC_ipd,
    SPMNeg      => SPMNeg_ipd,
    WRA         => WRA_ipd,
    WENC        => WENC_ipd);
    
  -- zero delayed outputs and bidirectional ports 
  -- (func. sec. uses these signals instead of =
  --  actual outputs and bidirectional ports);
  -- actual outputs are assigned in Path Delay Section
  
  SIGNAL A_zd         : std_logic_vector (35 downto 0);
  SIGNAL B_zd         : std_logic_vector (17 downto 0); 
  SIGNAL AEANeg_zd    : std_logic; 
  SIGNAL AEBNeg_zd    : std_logic;  
  SIGNAL AFANeg_zd    : std_logic;  
  SIGNAL AFCNeg_zd    : std_logic;  
  SIGNAL EFAORA_zd    : std_logic;     
  SIGNAL EFBORB_zd    : std_logic;     
  SIGNAL FFAIRA_zd    : std_logic;     
  SIGNAL FFCIRC_zd    : std_logic;     
  SIGNAL MBF1Neg_zd   : std_logic;    
  SIGNAL MBF2Neg_zd   : std_logic;   

  ------------------------------------------------------------------------------
  -- FIFO memory definitions
  ------------------------------------------------------------------------------
  -- general
  CONSTANT FIFOWordLength  :  positive := 36;
  SUBTYPE  FIFOWord    IS std_logic_vector(FIFOWordLength - 1 DOWNTO 0);
  TYPE     FIFOArray   IS ARRAY (0 TO FIFOSize - 1) OF FIFOWord;
  
  CONSTANT MailWordLength  :  positive := 18;
  SUBTYPE  MailWord    IS std_logic_vector(MailWordLength - 1 DOWNTO 0);
  
  CONSTANT Offs_Par_Number :  positive := 4; -- Number of Words while
  					     -- Parallel Offset Loading
  CONSTANT Offs_Ser_Number :  positive := OffsetSize*4; -- Number of Bits while
  					     -- Serial Offset Loading
  
  -- special
  CONSTANT FIFOWordBytes   :  positive := 4;
  
  ------------------------------------------------------------------------------
  -- internal constants 
  ------------------------------------------------------------------------------
  
     CONSTANT SIZByte : std_logic := '1';	
     CONSTANT SIZWord : std_logic := '0';    
  
  ------------------------------------------------------------------------------
  -- internal signals 
  ------------------------------------------------------------------------------ 

  -- FIFO Arrays
  
     SIGNAL FIFOMemory1int : FIFOArray := (FIFOArray'range =>
                                        FIFOWord'(OTHERS => 'X'));
     SIGNAL FIFOMemory2int : FIFOArray := (FIFOArray'range =>
                                        FIFOWord'(OTHERS => 'X'));
                                        
  -- Main Registers                                       
  
     -- Input Registers
      
     SIGNAL InputReg1int   : FIFOWord := (OTHERS => 'X');
     SIGNAL InputReg2int   : FIFOWord := (OTHERS => 'X'); 
     
     -- Output Registers
      
     SIGNAL OutputReg1int  : FIFOWord := (OTHERS => 'X');
     SIGNAL OutputReg2int  : FIFOWord := (OTHERS => 'X');
     
     -- FIFO Pointers
     
     SIGNAL ReadPtr1int    : Natural RANGE 0 TO FIFOSize-1;
     SIGNAL ReadPtr2int    : Natural RANGE 0 TO FIFOSize-1;
     SIGNAL WritePtr1int   : Natural RANGE 0 TO FIFOSize-1;
     SIGNAL WritePtr2int   : Natural RANGE 0 TO FIFOSize-1;
     
     -- FIFO Offset for Almoust Empty/Full Flags
     
     SIGNAL X1int, X2int,
            Y1int, Y2int   : Natural RANGE 0 TO FIFOSize-1;
     
     -- Mail Registers
     
     SIGNAL Mail1int,
            Mail2int       : MailWord := (OTHERS => 'X');
            
     -- Flags for Standart and FWFT mode
     
     SIGNAL EFANegint, EFBNegint, FFANegint, FFCNegint,	-- standard mode 
     	    ORAint, ORBint				-- FWFT mode
     	    : std_ulogic;    

     -- Flags Flip-flop first stage (each flag is synchonized 
     -- to its Port Clock through two flip-flop stages)
     
     SIGNAL EFA1int, EFB1int, FFA1int, FFC1int, 
            AEA1int, AEB1int, AFA1int, AFC1int : std_ulogic;
      
     ---------- Input Registers Controlling Signals ------------      
     -- Flags "Input Register is loaded" - in this 
     -- model they will be loaded to FIFOMemory on CLK negedge      
      
     SIGNAL InputReg1Readyint   : std_ulogic; 
     SIGNAL InputReg2Readyint   : std_ulogic; 
     SIGNAL InputReg2ReadyNextint   : std_ulogic; 
     
     -- Pointer for Byte/Word Access for PortB
     SIGNAL InputReg2Ptrint  : Natural RANGE 0 TO FIFOWordBytes-1;
     
     ---------- Output Registers Controlling Signals ------------      
     SIGNAL OutputReg1Readyint : std_ulogic; -- all 4-bytes have been
     				 	    -- read to Port-B 
     SIGNAL OutputReg1ReadyNextint : std_ulogic;
                                            -- all 4-bytes will be 
     				 	    -- read to Port-B next CLKB
     				 	    -- posedge
     -- Pointers for Byte/Word Access for PortB/PortC
        
     SIGNAL OutputReg1Ptrint : Natural RANGE 0 TO FIFOWordBytes-1;
     
       -- Pointers for Byte/Word Access that will be latched on CLKB posedge
       	     						   
       SIGNAL OutputReg1PtrNextint   : Natural RANGE 0 TO FIFOWordBytes - 1;
         
     SIGNAL OutputReg2Readyint : std_ulogic; -- word have been read to Port-A
     
     SIGNAL FWFTFirst : std_ulogic; -- first word though in FWFT mode
     
     -------------------------------------------------------------------------  
     -- Master Reset 1,2 / Partial Reset 1,2
     
     SIGNAL RST1int, RST2int: std_ulogic; 
                        -- MRS1Neg AND PRS1Neg; MRS2Neg AND PRS2Neg
     
     -- Master Reset (MRS1Neg = '0' and MRS2Neg = '0') done
     
     SIGNAL MRSDoneint: std_ulogic := '0';
     
     -- "Simultaneous Master Reset"
   
     SIGNAL  MRSint: std_ulogic;
     
     -- Counters of Clocks during Master/Partion Reset is active or just after
     -- Reset
     
     SIGNAL CountCLKA1int, CountCLKA2int, CountCLKBint, CountCLKCint: Natural;
     
     -- MRS1Neg, MRS2Neg states on CLKA posedge 
     
     SIGNAL MRS1CLKAint, MRS2CLKAint: std_ulogic;
     
     -- Big Endian ('1') / Little Endian ('0') Mode
     
     SIGNAL BEint: std_ulogic;
     
     -- Internal Control Signals
     
     SIGNAL EnWrFIFO1int, EnRdFIFO1int, EnWrFIFO2int, EnRdFIFO2int,
     	    EnWrMail1int, EnRdMail1int, EnWrMail2int, EnRdMail2int: std_ulogic; 
     	    
     ----------------------------------------------------------------------------
     -- ALmost-Empty/Almost-Full Offsets Loading Mode
     
     SIGNAL Offs_Par_Load_Modeint : bit := '0'; -- Parallel Offsets Loading Mode
     SIGNAL Offs_Ser_Load_Modeint : bit := '0'; -- Serial Offsets Loading Mode
     
     -- Word/Bit Counter while Offset Loading
     
     SIGNAL CountLoadOffsetint: Natural; 
     
     ----------------------------------------------------------------------------
     -- Additional Signals
     
     SIGNAL SIZBint, SIZCint: std_ulogic;
  
  BEGIN -- VitalBehavior block
     
--------------------------------------------------------------------------------
-- Timing Check Section                                                         
--------------------------------------------------------------------------------

     TimingChecks: PROCESS ( A_ipd, BEFWFT, C, CLKA, CLKB, CLKC, CSANeg, CSBNeg,
       ENA, FS0SD, FS1SEN, MBA, MBB, MBC, MRS1Neg, MRS2Neg, PRS1Neg, PRS2Neg,
       RENB, SIZEB, SIZEC, SPMNeg, WRA, WENC)

    -- Timing Check Variables

    -- Pulse Width Check Variables
      VARIABLE Pviol_CLKA          : X01 := '0';
      VARIABLE PD_CLKA             : VitalPeriodDataType := VitalPeriodDataInit;

      VARIABLE Pviol_CLKB          : X01 := '0';
      VARIABLE PD_CLKB             : VitalPeriodDataType := VitalPeriodDataInit;

      VARIABLE Pviol_CLKC          : X01 := '0';
      VARIABLE PD_CLKC             : VitalPeriodDataType := VitalPeriodDataInit;
    
    -- Setup/Hold Check Variables
      VARIABLE Tviol_A0_CLKA       : X01 := '0';
      VARIABLE TD_A0_CLKA          : VitalTimingDataType;

      VARIABLE TViol_C0_CLKC       : X01 := '0';
      VARIABLE TD_C0_CLKC          : VitalTimingDataType;

      VARIABLE Tviol_CSANeg_CLKA   : X01 := '0';
      VARIABLE TD_CSANeg_CLKA      : VitalTimingDataType;

      VARIABLE Tviol_WRA_CLKA      : X01 := '0';
      VARIABLE TD_WRA_CLKA         : VitalTimingDataType;

      VARIABLE Tviol_ENA_CLKA      : X01 := '0';
      VARIABLE TD_ENA_CLKA         : VitalTimingDataType;

      VARIABLE Tviol_MBA_CLKA      : X01 := '0';
      VARIABLE TD_MBA_CLKA         : VitalTimingDataType;

      VARIABLE Tviol_RENB_CLKB     : X01 := '0';
      VARIABLE TD_RENB_CLKB        : VitalTimingDataType;

      VARIABLE Tviol_MBB_CLKB      : X01 := '0';
      VARIABLE TD_MBB_CLKB         : VitalTimingDataType;

      VARIABLE Tviol_WENC_CLKC     : X01 := '0';
      VARIABLE TD_WENC_CLKC        : VitalTimingDataType;
    
      VARIABLE Tviol_MBC_CLKC      : X01 := '0';
      VARIABLE TD_MBC_CLKC         : VitalTimingDataType;
    
      VARIABLE Tviol_MRS1Neg_CLKA  : X01 := '0';
      VARIABLE TD_MRS1Neg_CLKA     : VitalTimingDataType;

      VARIABLE Tviol_MRS1Neg_CLKB  : X01 := '0';
      VARIABLE TD_MRS1Neg_CLKB     : VitalTimingDataType;

      VARIABLE Tviol_MRS2Neg_CLKA  : X01 := '0';
      VARIABLE TD_MRS2Neg_CLKA     : VitalTimingDataType;

      VARIABLE Tviol_MRS2Neg_CLKC  : X01 := '0';
      VARIABLE TD_MRS2Neg_CLKC     : VitalTimingDataType;

      VARIABLE Tviol_PRS1Neg_CLKA  : X01 := '0';
      VARIABLE TD_PRS1Neg_CLKA     : VitalTimingDataType;

      VARIABLE Tviol_PRS1Neg_CLKB  : X01 := '0';
      VARIABLE TD_PRS1Neg_CLKB     : VitalTimingDataType;

      VARIABLE Tviol_PRS2Neg_CLKA  : X01 := '0';
      VARIABLE TD_PRS2Neg_CLKA     : VitalTimingDataType;

      VARIABLE Tviol_PRS2Neg_CLKC  : X01 := '0';
      VARIABLE TD_PRS2Neg_CLKC     : VitalTimingDataType;