📄 cy7c453.vhd
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END IF; END IF; END IF; IF Start = '1' THEN -- Read/Write Cycles DataReg := Data; -- Write Cycle IF rising_edge(CKW) AND ENWNeg ='0' THEN IF wr_stat=act AND NOT wr_inhibit THEN IF parity_enable THEN IF parity_generate THEN DataReg := GenParity(Data,parity_odd_even,8); ELSE check_parity:=CheckParity(Data, parity_odd_even,9); IF check_parity=Data(8) THEN DataReg(8) := '1'; ELSE DataReg(8) :='0'; END IF; END IF; END IF; IF Violation ='0' THEN FIFOMemory( WritePointer ) := to_nat(DataReg); ELSE FIFOMemory( WritePointer ) := -1; END IF; IF WritePointer < FIFOSize THEN WritePointer <=WritePointer + 1; ELSE WritePointer <=0; END IF; CountPointer <= CountPointer + 1; IF CountPointer > (FIFOSize - FullOffReg - 1) THEN IF tSKEW_CKR_CKW >= tSKEW2 THEN XONeg_zd <= '0'; ELSE XONeg_zd <= '0' AFTER (tCKW); END IF; END IF; IF CountPointer = FIFOSize - 1 THEN IF tSKEW_CKR_CKW >= tSKEW1 THEN ENeg_zd <= '0'; ELSE ENeg_zd <= '0' AFTER (tCKW); END IF; wr_inhibit := TRUE; END IF; IF CountPointer < FIFOSize/2 - 1 THEN IF tSKEW_CKR_CKW >= tSKEW1 THEN HFNeg_zd <= '1'; ELSE HFNeg_zd <= '1' AFTER (tCKW); END IF; ELSE IF tSKEW_CKR_CKW >= tSKEW1 THEN HFNeg_zd <= '0'; ELSE HFNeg_zd <= '0' AFTER (tCKW); END IF; END IF; IF fifo_mode/=single THEN IF CountPointer = FIFOSize - 1 THEN IF tSKEW_CKR_CKW >= tSKEW2 THEN XONeg_zd <= '0'; ELSE XONeg_zd <= '0' AFTER (tCKW); END IF; ELSE IF tSKEW_CKR_CKW >= tSKEW2 THEN XONeg_zd <= '1'; ELSE XONeg_zd <= '1' AFTER (tCKW); END IF; END IF; END IF; END IF; END IF; -- End of Write Cycle -- Read Cycle IF rising_edge(CKR) AND ENRNeg = '0' THEN IF rd_stat=act THEN wr_inhibit := FALSE; IF ReadPointer= FIFOSize THEN ReadPointer<=0; ELSE ReadPointer<=ReadPointer + 1; END IF; CountPointer <= CountPointer - 1; IF CountPointer = 1 THEN rd_stat := inact; IF tSKEW_CKW_CKR >= tSKEW1 THEN ENeg_zd <= '0'; ELSE ENeg_zd <= '0' AFTER (tCKR); END IF; ELSE IF tSKEW_CKW_CKR >= tSKEW1 THEN ENeg_zd <= '1'; ELSE ENeg_zd <= '1' AFTER (tCKR); END IF; END IF; IF fifo_mode = single THEN IF CountPointer <= EmptyOffReg + 1 THEN IF tSKEW_CKW_CKR >= tSKEW2 THEN XONeg_zd <= '0'; ELSE XONeg_zd <= '0' AFTER (tCKR); END IF; ELSE IF tSKEW_CKW_CKR >= tSKEW2 THEN XONeg_zd <= '1'; ELSE XONeg_zd <= '1' AFTER (tCKR); END IF; END IF; END IF; IF fifo_mode /= single AND CountPointer = 0 THEN IF tSKEW_CKW_CKR >= tSKEW2 THEN XONeg_zd <= '1'; ELSE XONeg_zd <= '1' AFTER (tCKR); END IF; rd_stat := inact; END IF; END IF; IF OENeg = '0' THEN IF (FIFOMemory(ReadPointer)>=0) THEN Q_zd <= to_slv(FIFOMemory(ReadPointer),9); ELSE Q_zd <= (OTHERS=>'X'); END IF; END IF; END IF; -- End of Read Cycle IF falling_edge(FLNeg) THEN -- Expansion Check IF XINeg='0' THEN ReadPointer <= 0; CountPointer <= WritePointer; IF CountPointer = 0 THEN IF tSKEW_CKR_CKW >= tSKEW1 THEN ENeg_zd <= '0'; ELSE ENeg_zd <= '0' AFTER (tCKW); END IF; IF tSKEW_CKR_CKW >= tSKEW1 THEN HFNeg_zd <= '1'; ELSE HFNeg_zd <= '0' AFTER (tCKW); END IF; IF tSKEW_CKR_CKW >= tSKEW2 THEN XONeg_zd <= '0'; ELSE XONeg_zd <= '0' AFTER (tCKR); END IF; ELSIF CountPointer < EmptyOffReg THEN IF tSKEW_CKR_CKW >= tSKEW1 THEN ENeg_zd <= '1'; ELSE ENeg_zd <= '1' AFTER (tCKW); END IF; IF tSKEW_CKR_CKW >= tSKEW1 THEN HFNeg_zd <= '1' ; ELSE HFNeg_zd <= '1' AFTER (tCKW); END IF; IF tSKEW_CKR_CKW >= tSKEW2 THEN XONeg_zd <= '0'; ELSE XONeg_zd <= '0' AFTER (tCKR); END IF; ELSIF CountPointer < FIFOSize/2 THEN IF tSKEW_CKR_CKW >= tSKEW1 THEN ENeg_zd <= '1'; ELSE ENeg_zd <= '1' AFTER (tCKW); END IF; IF tSKEW_CKR_CKW >= tSKEW1 THEN HFNeg_zd <= '0' ; ELSE HFNeg_zd <= '0' AFTER (tCKW); END IF; IF tSKEW_CKR_CKW >= tSKEW2 THEN XONeg_zd <= '1'; ELSE XONeg_zd <= '1' AFTER (tCKR); END IF; ELSIF CountPointer < FIFOSize-FullOffReg THEN IF tSKEW_CKR_CKW >= tSKEW1 THEN ENeg_zd <= '1'; ELSE ENeg_zd <= '1' AFTER (tCKW); END IF; IF tSKEW_CKR_CKW >= tSKEW1 THEN HFNeg_zd <= '0' ; ELSE HFNeg_zd <= '0' AFTER (tCKW); END IF; IF tSKEW_CKR_CKW >= tSKEW2 THEN XONeg_zd <= '1'; ELSE XONeg_zd <= '1' AFTER (tCKR); END IF; ELSIF CountPointer < FIFOSize THEN IF tSKEW_CKR_CKW >= tSKEW1 THEN ENeg_zd <= '1'; ELSE ENeg_zd <= '1' AFTER (tCKW); END IF; IF tSKEW_CKR_CKW >= tSKEW1 THEN HFNeg_zd <= '0' ; ELSE HFNeg_zd <= '0' AFTER (tCKW); END IF; IF tSKEW_CKR_CKW >= tSKEW2 THEN XONeg_zd <= '1'; ELSE XONeg_zd <= '1' AFTER (tCKR); END IF; ELSE IF tSKEW_CKR_CKW >= tSKEW1 THEN ENeg_zd <= '0'; ELSE ENeg_zd <= '0' AFTER (tCKW); END IF; IF tSKEW_CKR_CKW >= tSKEW1 THEN HFNeg_zd <= '0' ; ELSE HFNeg_zd <= '0' AFTER (tCKW); END IF; IF tSKEW_CKR_CKW >= tSKEW2 THEN XONeg_zd <= '0'; ELSE XONeg_zd <= '0' AFTER (tCKR); END IF; END IF; ELSE IF ENWNeg='1' AND ENRNeg='1' THEN ReadPointer <= 0; -- Retransmit END IF; END IF; ELSIF falling_edge(XINeg) AND fifo_mode = other_exp THEN IF wr_stat = inact THEN wr_stat := act; ELSE rd_stat := act; END IF; END IF; -- End of Expansion Checking IF rising_edge(OENeg) THEN Q_zd <= ( OTHERS => 'Z' ); END IF; END IF; -- End of Start END PROCESS MainReadWrite; ------------------------------------------------------------------------ -- Detection of the actual tSKEW vals -- ------------------------------------------------------------------------ SkewDetector: PROCESS(CKR, CKW) VARIABLE tCKRposedge : Time := 0 ns; VARIABLE tCKWposedge : Time := 0 ns; BEGIN IF CKR'event AND CKR = '1' THEN tCKRposedge := Now; tSKEW_CKW_CKR <= Now - tCKWposedge; END IF; IF CKW'event AND CKW = '1' THEN tCKWposedge := Now; tSKEW_CKR_CKW <= Now - tCKRposedge; END IF; END PROCESS SkewDetector; ------------------------------------------------------------------------ -- Path delay section -- ------------------------------------------------------------------------ -- path delay for ENeg EFPathDelay: PROCESS (ENeg_zd) VARIABLE ENeg_GlitchData : VitalGlitchDataType; BEGIN VitalPathDelay01 (OutSignal => ENeg, OutSignalName => "ENeg", OutTemp => ENeg_zd, GlitchData => ENeg_GlitchData, Paths => (0 => (InputChangeTime => MRNeg'LAST_EVENT, PathDelay => tpd_MRNeg_ENeg, PathCondition => true), 1 => (InputChangeTime => CKR'LAST_EVENT, PathDelay => tpd_CKW_ENeg, PathCondition => true), 2 => (InputChangeTime => CKW'LAST_EVENT, PathDelay => tpd_CKW_ENeg, PathCondition => true))); END PROCESS EFPathDelay; -- path delay for XONeg PAEPathDelay: PROCESS (XONeg_zd) VARIABLE XONeg_GlitchData : VitalGlitchDataType; BEGIN VitalPathDelay01 (OutSignal => XONeg, OutSignalName => "XONeg", OutTemp => XONeg_zd, GlitchData => XONeg_GlitchData, Paths => (0 => (InputChangeTime => MRNeg'LAST_EVENT, PathDelay => tpd_MRNeg_ENeg, PathCondition => true), 1 => (InputChangeTime => CKR'LAST_EVENT, PathDelay => tpd_CKW_ENeg, PathCondition => true), 2 => (InputChangeTime => CKW'LAST_EVENT, PathDelay => tpd_CKW_ENeg, PathCondition => true))); END PROCESS PAEPathDelay; -- path delay for HFNeg HFPathDelay: PROCESS (HFNeg_zd) VARIABLE HFNeg_GlitchData : VitalGlitchDataType; BEGIN VitalPathDelay01 (OutSignal => HFNeg, OutSignalName => "HFNeg", OutTemp => HFNeg_zd, GlitchData => HFNeg_GlitchData, Paths => (0 => (InputChangeTime => MRNeg'LAST_EVENT, PathDelay => tpd_MRNeg_ENeg, PathCondition => true), 1 => (InputChangeTime => CKW'LAST_EVENT, PathDelay => tpd_CKW_ENeg, PathCondition => true))); END PROCESS HFPathDelay; -- path delay for ENeg QPathDelay_Gen: FOR i IN FIFOWordLenght-1 DOWNTO 0 GENERATE PROCESS (Q_zd(i)) VARIABLE Q_GlitchData : VitalGlitchDataType; BEGIN VitalPathDelay01Z (OutSignal => Q(i), OutSignalName => "Q", OutTemp => Q_zd(i), GlitchData => Q_GlitchData, Paths =>(0 =>(InputChangeTime => MRNeg'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_MRNeg_Q0), PathCondition =>true), 1 =>(InputChangeTime => CKR'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_CKR_Q0), PathCondition =>true), 2 =>(InputChangeTime =>OENeg'LAST_EVENT, PathDelay =>tpd_OENeg_Q0, PathCondition =>TRUE))); END PROCESS; END GENERATE QPathDelay_Gen; END BLOCK VitalBehavior;END vhdl_behavioral;⌨️ 快捷键说明
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